From patchwork Mon Mar 7 15:01:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Pandey X-Patchwork-Id: 51736 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F55B3857C51 for ; Mon, 7 Mar 2022 16:33:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1F55B3857C51 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1646670789; bh=10iQzV6D6lqbqhv7cDj4LPgMHR0AsIGQ7L7+xM3NXRs=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=KwG8ZSxYsAbC2znpiNo78bw8aQVv4gXS0WX+aGVEjSl6wvl7UOg3ao+GR0qznVmDh 7/CwT91WEBun5KPvHG01Ax7QoMwSrC8GUCoTN+Xzs6z/EbKOVL4r72S3vA4n8dWhyv d3pVhxZOuOIefL3hqaA72nllfR8NHSAKakmUFsLM= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id C691D3858004 for ; Mon, 7 Mar 2022 15:03:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C691D3858004 X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="234364161" X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="234364161" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 07:02:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="643274109" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 07 Mar 2022 07:02:10 -0800 Received: from gskx-1.sc.intel.com (gskx-1.sc.intel.com [172.25.149.211]) by scymds01.sc.intel.com with ESMTP id 227F21fH016772; Mon, 7 Mar 2022 07:02:09 -0800 To: libc-alpha@sourceware.org Subject: [PATCH 103/126] x86_64: Fix svml_s_log2f16_core_avx512.S code formatting Date: Mon, 7 Mar 2022 07:01:38 -0800 Message-Id: <20220307150201.10590-104-skpgkp2@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220307150201.10590-1-skpgkp2@gmail.com> References: <20220307150201.10590-1-skpgkp2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FORGED_GMAIL_RCVD, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HK_RANDOM_ENVFROM, HK_RANDOM_FROM, KAM_DMARC_NONE, KAM_DMARC_STATUS, NML_ADSP_CUSTOM_MED, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Sunil K Pandey via Libc-alpha From: Sunil Pandey Reply-To: Sunil K Pandey Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit contains following formatting changes 1. Instructions proceeded by a tab. 2. Instruction less than 8 characters in length have a tab between it and the first operand. 3. Instruction greater than 7 characters in length have a space between it and the first operand. 4. Tabs after `#define`d names and their value. 5. 8 space at the beginning of line replaced by tab. 6. Indent comments with code. 7. Remove redundent .text section. --- .../multiarch/svml_s_log2f16_core_avx512.S | 347 +++++++++--------- 1 file changed, 173 insertions(+), 174 deletions(-) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core_avx512.S index bf58c6bcf7..3b0a28fee0 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core_avx512.S @@ -29,203 +29,202 @@ /* Offsets for data table __svml_slog2_data_internal_avx512 */ -#define One 0 -#define coeff4 64 -#define coeff3 128 -#define coeff2 192 -#define coeff1 256 +#define One 0 +#define coeff4 64 +#define coeff3 128 +#define coeff2 192 +#define coeff1 256 #include - .text - .section .text.exex512,"ax",@progbits + .section .text.exex512, "ax", @progbits ENTRY(_ZGVeN16v_log2f_skx) - pushq %rbp - cfi_def_cfa_offset(16) - movq %rsp, %rbp - cfi_def_cfa(6, 16) - cfi_offset(6, -16) - andq $-64, %rsp - subq $192, %rsp - vgetmantps $11, {sae}, %zmm0, %zmm3 - vmovups __svml_slog2_data_internal_avx512(%rip), %zmm1 - vgetexpps {sae}, %zmm0, %zmm5 - -/* x<=0? */ - vfpclassps $94, %zmm0, %k0 - vsubps {rn-sae}, %zmm1, %zmm3, %zmm9 - vpsrld $19, %zmm3, %zmm7 - vgetexpps {sae}, %zmm3, %zmm6 - vpermps coeff4+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm1 - vpermps coeff3+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm2 - vpermps coeff2+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm4 - vpermps coeff1+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm8 - vsubps {rn-sae}, %zmm6, %zmm5, %zmm10 - vfmadd213ps {rn-sae}, %zmm2, %zmm9, %zmm1 - kmovw %k0, %edx - vfmadd213ps {rn-sae}, %zmm4, %zmm9, %zmm1 - vfmadd213ps {rn-sae}, %zmm8, %zmm9, %zmm1 - vfmadd213ps {rn-sae}, %zmm10, %zmm9, %zmm1 - testl %edx, %edx - -/* Go to special inputs processing branch */ - jne L(SPECIAL_VALUES_BRANCH) - # LOE rbx r12 r13 r14 r15 edx zmm0 zmm1 - -/* Restore registers - * and exit the function - */ + pushq %rbp + cfi_def_cfa_offset(16) + movq %rsp, %rbp + cfi_def_cfa(6, 16) + cfi_offset(6, -16) + andq $-64, %rsp + subq $192, %rsp + vgetmantps $11, {sae}, %zmm0, %zmm3 + vmovups __svml_slog2_data_internal_avx512(%rip), %zmm1 + vgetexpps {sae}, %zmm0, %zmm5 + + /* x<=0? */ + vfpclassps $94, %zmm0, %k0 + vsubps {rn-sae}, %zmm1, %zmm3, %zmm9 + vpsrld $19, %zmm3, %zmm7 + vgetexpps {sae}, %zmm3, %zmm6 + vpermps coeff4+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm1 + vpermps coeff3+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm2 + vpermps coeff2+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm4 + vpermps coeff1+__svml_slog2_data_internal_avx512(%rip), %zmm7, %zmm8 + vsubps {rn-sae}, %zmm6, %zmm5, %zmm10 + vfmadd213ps {rn-sae}, %zmm2, %zmm9, %zmm1 + kmovw %k0, %edx + vfmadd213ps {rn-sae}, %zmm4, %zmm9, %zmm1 + vfmadd213ps {rn-sae}, %zmm8, %zmm9, %zmm1 + vfmadd213ps {rn-sae}, %zmm10, %zmm9, %zmm1 + testl %edx, %edx + + /* Go to special inputs processing branch */ + jne L(SPECIAL_VALUES_BRANCH) + # LOE rbx r12 r13 r14 r15 edx zmm0 zmm1 + + /* Restore registers + * and exit the function + */ L(EXIT): - vmovaps %zmm1, %zmm0 - movq %rbp, %rsp - popq %rbp - cfi_def_cfa(7, 8) - cfi_restore(6) - ret - cfi_def_cfa(6, 16) - cfi_offset(6, -16) - -/* Branch to process - * special inputs - */ + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + popq %rbp + cfi_def_cfa(7, 8) + cfi_restore(6) + ret + cfi_def_cfa(6, 16) + cfi_offset(6, -16) + + /* Branch to process + * special inputs + */ L(SPECIAL_VALUES_BRANCH): - vmovups %zmm0, 64(%rsp) - vmovups %zmm1, 128(%rsp) - # LOE rbx r12 r13 r14 r15 edx zmm1 - - xorl %eax, %eax - # LOE rbx r12 r13 r14 r15 eax edx - - vzeroupper - movq %r12, 16(%rsp) - /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */ - .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22 - movl %eax, %r12d - movq %r13, 8(%rsp) - /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */ - .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22 - movl %edx, %r13d - movq %r14, (%rsp) - /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */ - .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22 - # LOE rbx r15 r12d r13d - -/* Range mask - * bits check - */ + vmovups %zmm0, 64(%rsp) + vmovups %zmm1, 128(%rsp) + # LOE rbx r12 r13 r14 r15 edx zmm1 + + xorl %eax, %eax + # LOE rbx r12 r13 r14 r15 eax edx + + vzeroupper + movq %r12, 16(%rsp) + /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */ + .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22 + movl %eax, %r12d + movq %r13, 8(%rsp) + /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */ + .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22 + movl %edx, %r13d + movq %r14, (%rsp) + /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */ + .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22 + # LOE rbx r15 r12d r13d + + /* Range mask + * bits check + */ L(RANGEMASK_CHECK): - btl %r12d, %r13d + btl %r12d, %r13d -/* Call scalar math function */ - jc L(SCALAR_MATH_CALL) - # LOE rbx r15 r12d r13d + /* Call scalar math function */ + jc L(SCALAR_MATH_CALL) + # LOE rbx r15 r12d r13d -/* Special inputs - * processing loop - */ + /* Special inputs + * processing loop + */ L(SPECIAL_VALUES_LOOP): - incl %r12d - cmpl $16, %r12d - -/* Check bits in range mask */ - jl L(RANGEMASK_CHECK) - # LOE rbx r15 r12d r13d - - movq 16(%rsp), %r12 - cfi_restore(12) - movq 8(%rsp), %r13 - cfi_restore(13) - movq (%rsp), %r14 - cfi_restore(14) - vmovups 128(%rsp), %zmm1 - -/* Go to exit */ - jmp L(EXIT) - /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */ - .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22 - /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */ - .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22 - /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */ - .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22 - # LOE rbx r12 r13 r14 r15 zmm1 - -/* Scalar math fucntion call - * to process special input - */ + incl %r12d + cmpl $16, %r12d + + /* Check bits in range mask */ + jl L(RANGEMASK_CHECK) + # LOE rbx r15 r12d r13d + + movq 16(%rsp), %r12 + cfi_restore(12) + movq 8(%rsp), %r13 + cfi_restore(13) + movq (%rsp), %r14 + cfi_restore(14) + vmovups 128(%rsp), %zmm1 + + /* Go to exit */ + jmp L(EXIT) + /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */ + .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22 + /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */ + .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22 + /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */ + .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22 + # LOE rbx r12 r13 r14 r15 zmm1 + + /* Scalar math fucntion call + * to process special input + */ L(SCALAR_MATH_CALL): - movl %r12d, %r14d - movss 64(%rsp,%r14,4), %xmm0 - call log2f@PLT - # LOE rbx r14 r15 r12d r13d xmm0 + movl %r12d, %r14d + movss 64(%rsp, %r14, 4), %xmm0 + call log2f@PLT + # LOE rbx r14 r15 r12d r13d xmm0 - movss %xmm0, 128(%rsp,%r14,4) + movss %xmm0, 128(%rsp, %r14, 4) -/* Process special inputs in loop */ - jmp L(SPECIAL_VALUES_LOOP) - # LOE rbx r15 r12d r13d + /* Process special inputs in loop */ + jmp L(SPECIAL_VALUES_LOOP) + # LOE rbx r15 r12d r13d END(_ZGVeN16v_log2f_skx) - .section .rodata, "a" - .align 64 + .section .rodata, "a" + .align 64 #ifdef __svml_slog2_data_internal_avx512_typedef typedef unsigned int VUINT32; typedef struct { - __declspec(align(64)) VUINT32 One[16][1]; - __declspec(align(64)) VUINT32 coeff4[16][1]; - __declspec(align(64)) VUINT32 coeff3[16][1]; - __declspec(align(64)) VUINT32 coeff2[16][1]; - __declspec(align(64)) VUINT32 coeff1[16][1]; - } __svml_slog2_data_internal_avx512; + __declspec(align(64)) VUINT32 One[16][1]; + __declspec(align(64)) VUINT32 coeff4[16][1]; + __declspec(align(64)) VUINT32 coeff3[16][1]; + __declspec(align(64)) VUINT32 coeff2[16][1]; + __declspec(align(64)) VUINT32 coeff1[16][1]; +} __svml_slog2_data_internal_avx512; #endif __svml_slog2_data_internal_avx512: - /*== One ==*/ - .long 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 - // c4 - .align 64 - .long 0xbea77e4a, 0xbe8aae3d - .long 0xbe67fe32, 0xbe43d1b6 - .long 0xbe26a589, 0xbe0ee09b - .long 0xbdf6a8a1, 0xbdd63b49 - .long 0xbf584e51, 0xbf3e80a1 - .long 0xbf2892f0, 0xbf15d377 - .long 0xbf05b525, 0xbeef8e30 - .long 0xbed75c8f, 0xbec24184 - // c3 - .align 64 - .long 0x3ef5910c, 0x3ef045a1 - .long 0x3ee7d87e, 0x3eddbb84 - .long 0x3ed2d6df, 0x3ec7bbd2 - .long 0x3ebcc42f, 0x3eb22616 - .long 0x3e8f3399, 0x3eb1223e - .long 0x3ec9db4a, 0x3edb7a09 - .long 0x3ee79a1a, 0x3eef77cb - .long 0x3ef407a4, 0x3ef607b4 - // c2 - .align 64 - .long 0xbf38a934, 0xbf387de6 - .long 0xbf37f6f0, 0xbf37048b - .long 0xbf35a88a, 0xbf33ed04 - .long 0xbf31df56, 0xbf2f8d82 - .long 0xbf416814, 0xbf3daf58 - .long 0xbf3b5c08, 0xbf39fa2a - .long 0xbf393713, 0xbf38d7e1 - .long 0xbf38b2cd, 0xbf38aa62 - // c1 - .align 64 - .long 0x3fb8aa3b, 0x3fb8a9c0 - .long 0x3fb8a6e8, 0x3fb89f4e - .long 0x3fb890cb, 0x3fb879b1 - .long 0x3fb858d8, 0x3fb82d90 - .long 0x3fb8655e, 0x3fb8883a - .long 0x3fb89aea, 0x3fb8a42f - .long 0x3fb8a848, 0x3fb8a9c9 - .long 0x3fb8aa2f, 0x3fb8aa3b - .align 64 - .type __svml_slog2_data_internal_avx512,@object - .size __svml_slog2_data_internal_avx512,.-__svml_slog2_data_internal_avx512 + /* One */ + .long 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + // c4 + .align 64 + .long 0xbea77e4a, 0xbe8aae3d + .long 0xbe67fe32, 0xbe43d1b6 + .long 0xbe26a589, 0xbe0ee09b + .long 0xbdf6a8a1, 0xbdd63b49 + .long 0xbf584e51, 0xbf3e80a1 + .long 0xbf2892f0, 0xbf15d377 + .long 0xbf05b525, 0xbeef8e30 + .long 0xbed75c8f, 0xbec24184 + // c3 + .align 64 + .long 0x3ef5910c, 0x3ef045a1 + .long 0x3ee7d87e, 0x3eddbb84 + .long 0x3ed2d6df, 0x3ec7bbd2 + .long 0x3ebcc42f, 0x3eb22616 + .long 0x3e8f3399, 0x3eb1223e + .long 0x3ec9db4a, 0x3edb7a09 + .long 0x3ee79a1a, 0x3eef77cb + .long 0x3ef407a4, 0x3ef607b4 + // c2 + .align 64 + .long 0xbf38a934, 0xbf387de6 + .long 0xbf37f6f0, 0xbf37048b + .long 0xbf35a88a, 0xbf33ed04 + .long 0xbf31df56, 0xbf2f8d82 + .long 0xbf416814, 0xbf3daf58 + .long 0xbf3b5c08, 0xbf39fa2a + .long 0xbf393713, 0xbf38d7e1 + .long 0xbf38b2cd, 0xbf38aa62 + // c1 + .align 64 + .long 0x3fb8aa3b, 0x3fb8a9c0 + .long 0x3fb8a6e8, 0x3fb89f4e + .long 0x3fb890cb, 0x3fb879b1 + .long 0x3fb858d8, 0x3fb82d90 + .long 0x3fb8655e, 0x3fb8883a + .long 0x3fb89aea, 0x3fb8a42f + .long 0x3fb8a848, 0x3fb8a9c9 + .long 0x3fb8aa2f, 0x3fb8aa3b + .align 64 + .type __svml_slog2_data_internal_avx512, @object + .size __svml_slog2_data_internal_avx512, .-__svml_slog2_data_internal_avx512