From patchwork Sat Mar 6 19:11:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 42361 X-Patchwork-Delegate: carlos@redhat.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 01363384A033; Sat, 6 Mar 2021 19:11:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 01363384A033 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1615057878; bh=jLsZFFkHdqXqhj8H7NeZWlq/FEHmUESBB7uPKl5n4I8=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=vSNPhi6kHqUG2XiEltCTKoUx/He/3jIqOSnPab0A5OO5jeubFny0z2CRmRB+wmHbA 6g3NZBlsJDcczQU6p+PIRVjK6EEbuc+eOZ6HpMO13U4m9iI9XOJkIzaFc9MCTUvpZK x5mYDXtzPJf3k3t2lWK5s+21NUu9kCtcWSJnYgfg= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by sourceware.org (Postfix) with ESMTPS id D4DC9385800C for ; Sat, 6 Mar 2021 19:11:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D4DC9385800C Received: by mail-pj1-x1033.google.com with SMTP id q2-20020a17090a2e02b02900bee668844dso899996pjd.3 for ; Sat, 06 Mar 2021 11:11:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=jLsZFFkHdqXqhj8H7NeZWlq/FEHmUESBB7uPKl5n4I8=; b=d1D1ItrRw0BpNJivdadP18P2sOBP+Sr9Ni5uvW0R8MdfGVSZGWuVTpi/HIuT54dRIu 0XXBQCbFeXKyy9qmdz/mZ9Cq/nSurb/KlpAzuj7xw6aQtdKGErSBxqfjF8F0f17ZB8Jz IM6hBj6com7cQ69Y8BZAsaam/zJJVGbESpPPv0KaBOrFNNh1q6TFo6m7e/NVi9An4lMC hfCKvjsN3jSiNoPI3b1QShHOMFlBTCpKYJwxmFza3ErI93N2JyXY6sN2yIqVw0o2NxiS wr0HwW33tLeIdqRcsUzL9EfuKW8sPS9gSfUmnYd1Taag3bK1shX+yF5Le5SEgMZPu9Hz 0iew== X-Gm-Message-State: AOAM530TWlyKVtXynWkhpIMc5bAYuwhBtBhK8gWCspAnGaArrxz3RRkg 1dws7ql3WGFB0zuSKHyBZ0M9VwSiHVg= X-Google-Smtp-Source: ABdhPJwkSSZJ5QuPYMlJz4uGTaJVFYvd7v+xiwAXQZQDWDrasfSdhbyhVZMsqd6/L1Xnve/7qgdWRQ== X-Received: by 2002:a17:902:b011:b029:e4:c22d:ac27 with SMTP id o17-20020a170902b011b02900e4c22dac27mr14349463plr.65.1615057873522; Sat, 06 Mar 2021 11:11:13 -0800 (PST) Received: from gnu-cfl-2.localdomain ([172.56.38.48]) by smtp.gmail.com with ESMTPSA id t6sm5755230pgp.57.2021.03.06.11.11.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 11:11:13 -0800 (PST) Received: from gnu-cfl-2.?040none?041 (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 9EA9A1A016E for ; Sat, 6 Mar 2021 11:11:11 -0800 (PST) To: libc-alpha@sourceware.org Subject: [PATCH] x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] Date: Sat, 6 Mar 2021 11:11:11 -0800 Message-Id: <20210306191111.1760885-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-Spam-Status: No, score=-3034.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" commit 2d651eb9265d1366d7b9e881bfddd46db9c1ecc4 Author: H.J. Lu Date: Fri Sep 18 07:55:14 2020 -0700 x86: Move x86 processor cache info to cpu_features missed _SC_LEVEL1_ICACHE_LINESIZE. 1. Add level1_icache_linesize to struct cpu_features. 2. Initialize level1_icache_linesize by calling handle_intel, handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE. 3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE. Reviewed-by: Carlos O'Donell --- sysdeps/x86/Makefile | 8 +++ sysdeps/x86/cacheinfo.c | 3 + sysdeps/x86/dl-cacheinfo.h | 6 ++ sysdeps/x86/dl-diagnostics-cpu.c | 2 + sysdeps/x86/include/cpu-features.h | 2 + .../x86/tst-sysconf-cache-linesize-static.c | 1 + sysdeps/x86/tst-sysconf-cache-linesize.c | 57 +++++++++++++++++++ 7 files changed, 79 insertions(+) create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize-static.c create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize.c diff --git a/sysdeps/x86/Makefile b/sysdeps/x86/Makefile index e1f9379fd8..06c9f84f51 100644 --- a/sysdeps/x86/Makefile +++ b/sysdeps/x86/Makefile @@ -211,3 +211,11 @@ $(objpfx)check-cet.out: $(..)sysdeps/x86/check-cet.awk \ generated += check-cet.out endif endif + +ifeq ($(subdir),posix) +tests += \ + tst-sysconf-cache-linesize \ + tst-sysconf-cache-linesize-static +tests-static += \ + tst-sysconf-cache-linesize-static +endif diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 7b8df45e3b..5ea4723ca6 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -32,6 +32,9 @@ __cache_sysconf (int name) case _SC_LEVEL1_ICACHE_SIZE: return cpu_features->level1_icache_size; + case _SC_LEVEL1_ICACHE_LINESIZE: + return cpu_features->level1_icache_linesize; + case _SC_LEVEL1_DCACHE_SIZE: return cpu_features->level1_dcache_size; diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index f3de206dc1..d9944250fc 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -707,6 +707,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) long int core = -1; unsigned int threads = 0; unsigned long int level1_icache_size = -1; + unsigned long int level1_icache_linesize = -1; unsigned long int level1_dcache_size = -1; unsigned long int level1_dcache_assoc = -1; unsigned long int level1_dcache_linesize = -1; @@ -726,6 +727,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) level1_icache_size = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); + level1_icache_linesize + = handle_intel (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features); level1_dcache_size = data; level1_dcache_assoc = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); @@ -753,6 +756,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); + level1_icache_linesize = handle_zhaoxin (_SC_LEVEL1_ICACHE_LINESIZE); level1_dcache_size = data; level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); @@ -772,6 +776,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); + level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE); level1_dcache_size = data; level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); @@ -833,6 +838,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) } cpu_features->level1_icache_size = level1_icache_size; + cpu_features->level1_icache_linesize = level1_icache_linesize; cpu_features->level1_dcache_size = level1_dcache_size; cpu_features->level1_dcache_assoc = level1_dcache_assoc; cpu_features->level1_dcache_linesize = level1_dcache_linesize; diff --git a/sysdeps/x86/dl-diagnostics-cpu.c b/sysdeps/x86/dl-diagnostics-cpu.c index 5d9713f8d9..5d04527ad1 100644 --- a/sysdeps/x86/dl-diagnostics-cpu.c +++ b/sysdeps/x86/dl-diagnostics-cpu.c @@ -91,6 +91,8 @@ _dl_diagnostics_cpu (void) cpu_features->rep_stosb_threshold); print_cpu_features_value ("level1_icache_size", cpu_features->level1_icache_size); + print_cpu_features_value ("level1_icache_linesize", + cpu_features->level1_icache_linesize); print_cpu_features_value ("level1_dcache_size", cpu_features->level1_dcache_size); print_cpu_features_value ("level1_dcache_assoc", diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index c5a779ba32..d042a2ebef 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -876,6 +876,8 @@ struct cpu_features unsigned long int rep_stosb_threshold; /* _SC_LEVEL1_ICACHE_SIZE. */ unsigned long int level1_icache_size; + /* _SC_LEVEL1_ICACHE_LINESIZE. */ + unsigned long int level1_icache_linesize; /* _SC_LEVEL1_DCACHE_SIZE. */ unsigned long int level1_dcache_size; /* _SC_LEVEL1_DCACHE_ASSOC. */ diff --git a/sysdeps/x86/tst-sysconf-cache-linesize-static.c b/sysdeps/x86/tst-sysconf-cache-linesize-static.c new file mode 100644 index 0000000000..152ae68821 --- /dev/null +++ b/sysdeps/x86/tst-sysconf-cache-linesize-static.c @@ -0,0 +1 @@ +#include "tst-sysconf-cache-linesize.c" diff --git a/sysdeps/x86/tst-sysconf-cache-linesize.c b/sysdeps/x86/tst-sysconf-cache-linesize.c new file mode 100644 index 0000000000..642dbde5d2 --- /dev/null +++ b/sysdeps/x86/tst-sysconf-cache-linesize.c @@ -0,0 +1,57 @@ +/* Test system cache line sizes. + Copyright (C) 2021 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include +#include +#include +#include + +static struct +{ + const char *name; + int _SC_val; +} sc_options[] = + { +#define N(name) { "_SC_"#name, _SC_##name } + N (LEVEL1_ICACHE_LINESIZE), + N (LEVEL1_DCACHE_LINESIZE), + N (LEVEL2_CACHE_LINESIZE) + }; + +static int +do_test (void) +{ + int result = EXIT_SUCCESS; + + for (int i = 0; i < array_length (sc_options); ++i) + { + long int scret = sysconf (sc_options[i]._SC_val); + if (scret < 0) + { + printf ("sysconf (%s) returned < 0 (%ld)\n", + sc_options[i].name, scret); + result = EXIT_FAILURE; + } + else + printf ("sysconf (%s): %ld\n", sc_options[i].name, scret); + } + + return result; +} + +#include