Message ID | 20201128081817.15463-2-huangpei@loongson.cn |
---|---|
State | Superseded |
Headers |
Return-Path: <libc-alpha-bounces@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 665B43851C1F; Sat, 28 Nov 2020 08:18:46 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 95ED13858C27 for <libc-alpha@sourceware.org>; Sat, 28 Nov 2020 08:18:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 95ED13858C27 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=huangpei@loongson.cn Received: from localhost.localdomain (unknown [182.149.161.68]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9AxetHVB8Jf7NEXAA--.15226S3; Sat, 28 Nov 2020 16:18:35 +0800 (CST) From: Huang Pei <huangpei@loongson.cn> To: Joseph Myers <joseph@codesourcery.com> Subject: [PATCH 1/3] mips: add hp-timing support for MIPS R2 Date: Sat, 28 Nov 2020 16:18:15 +0800 Message-Id: <20201128081817.15463-2-huangpei@loongson.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201128081817.15463-1-huangpei@loongson.cn> References: <20201128081817.15463-1-huangpei@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf9AxetHVB8Jf7NEXAA--.15226S3 X-Coremail-Antispam: 1UD129KBjvJXoW7CFWxCrW7ZF43Gw4kuF1kGrg_yoW8tr1fpF 48CF15GF4vqrWak3yfAa13GF1rtFs5JF1rGF13CFW5Jwn8JFy0qrZFvrW5K34xJryfur97 ZFs7uFWUCFs7AFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBq14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1Y6r1xM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8ZwCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbSdgJUUUUU== X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> Cc: Huacai Chen <chenhc@lemote.com>, Chenghua Xu <xuchenghua@loongson.cn>, libc-alpha <libc-alpha@sourceware.org> Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces@sourceware.org> |
Series |
[1/3] mips: add hp-timing support for MIPS R2
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Commit Message
Huang Pei
Nov. 28, 2020, 8:18 a.m. UTC
MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
enough for glibc.
DO remember Linux/MIPS added emulation for 'rdhwr %0, $2',when disabled
or not supported, which would make the precision worse. If you got
unreasonable result, check your CPU Manual for whether your CPU
implemnted it or not
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
sysdeps/mips/hp-timing.h | 43 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 sysdeps/mips/hp-timing.h
Comments
On 28/11/2020 05:18, Huang Pei wrote: > MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be > enough for glibc. > > DO remember Linux/MIPS added emulation for 'rdhwr %0, $2',when disabled > or not supported, which would make the precision worse. If you got > unreasonable result, check your CPU Manual for whether your CPU > implemnted it or not It seems that rdhwr trap simulation has been on kernel since 2.6.15-rc1 (3c37026d43c47be), so it should be safe to assume current minimum kernel support for it. However it does not only make the precision worse, but a missing rdwhr support would also slow down the loader since the hp-timing support is assumed to be 'fast' and loader code will use it regardless LD_DEBUG=statistics is set or not. It should be suffice to enabled it iff __mips_isa_rev is higher than 2, but do you know if there ARE chips which implement ISA higher than r2 that do not support this instruction? If so, how common are they? > > Signed-off-by: Huang Pei <huangpei@loongson.cn> We do not use SCO, but rather Copyright assignments. > --- > sysdeps/mips/hp-timing.h | 43 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 sysdeps/mips/hp-timing.h > > diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h > new file mode 100644 > index 0000000000..128315d0bf > --- /dev/null > +++ b/sysdeps/mips/hp-timing.h > @@ -0,0 +1,43 @@ > +/* High precision, low overhead timing functions. MIPS version. > + Copyright (C) 2002-2020 Free Software Foundation, Inc. I think it should be on 2020. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + <http://www.gnu.org/licenses/>. */ > + > +#ifndef _HP_TIMING_H > +#define _HP_TIMING_H 1 > + > +#if __mips_isa_rev >= 2 > +/* We always assume having the timestamp register. */ > +#define HP_TIMING_AVAIL (0) > +#define HP_SMALL_TIMING_AVAIL (1) It seems to be based on a older glibc version, the hp-timing.h has been refactored on 2.30 (1e372ded4f83362) and since then simplified a bit. Please check the generic interface 'sysdeps/generic/hp-timing.h' to see how to proceed it. For instance, alpha has a similar constraint where its timestamp register only has 4s range and then it is only enabled for ld.so statistics. I am not sure which the usual frequency for mips chips, so maybe we should also enable it only for loader (since using it on benchmarks might get us bogus value due overflow). So you might need to do something like: #if IS_IN(rtld) && __mips_isa_rev >= 2 typedef unsigned int hp_timing_t; # define HP_TIMING_NOW(Var) \ ({ unsigned int _count; \ asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \ (Var) = _count; }) #else # include <sysdeps/generic/hp-timing.h> #endif Also, the generic implementation uses clock_gettime and which a recent kernel it will use the vDSO and thus reducing latency). > + > +/* We indeed have inlined functions. */ > +#define HP_TIMING_INLINE (1) > + > +/* We use 32bit values for the times. */ > +typedef unsigned int hp_timing_t; > + > +/* Read the cp0 count, this maybe inaccurate. */ > +#define HP_TIMING_NOW(Var) \ > + ({ unsigned int _count; \ > + asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \ > + (Var) = _count; }) > + > +#include <hp-timing-common.h> > + > +#endif > + > +#endif /* hp-timing.h */ >
On Mon, 30 Nov 2020, Adhemerval Zanella via Libc-alpha wrote: > > MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be > > enough for glibc. > > > > DO remember Linux/MIPS added emulation for 'rdhwr %0, $2',when disabled > > or not supported, which would make the precision worse. If you got > > unreasonable result, check your CPU Manual for whether your CPU > > implemnted it or not > > It seems that rdhwr trap simulation has been on kernel since 2.6.15-rc1 > (3c37026d43c47be), so it should be safe to assume current minimum kernel > support for it. Nope, that was commit 1f5826bd0ed6c ("[MIPS] Added missing cases for rdhwr emulation") and Linux 2.6.25 respectively. The other commit only added User Local Register (ULR) access emulation for TLS pointer access. Also CP0 Counter (CC) register access emulation relies on `read_c0_count', which is NOT universally supported, as not all MIPS CPUs have the CC, in which case rubbish will be returned (the relevant instruction does not trap on invalid CP0 register accesses). None of this seems to matter however if we only handle this for R2 and higher ISA versions where both the CC and RDHWR are required by the architecture. > However it does not only make the precision worse, but a missing rdwhr > support would also slow down the loader since the hp-timing support is > assumed to be 'fast' and loader code will use it regardless > LD_DEBUG=statistics is set or not. It should be suffice to enabled it > iff __mips_isa_rev is higher than 2, but do you know if there ARE chips > which implement ISA higher than r2 that do not support this instruction? > If so, how common are they? The RDHWR instruction is mandatory, though access to individual registers is controlled by the kernel, via the CP0 HWREna register bitmask. We have had access enabled to registers 3:0 (CC is $2) unconditionally however: if (cpu_has_mips_r2_r6) hwrena |= MIPS_HWRENA_CPUNUM | MIPS_HWRENA_SYNCISTEP | MIPS_HWRENA_CC | MIPS_HWRENA_CCRES; ever since commit e01402b115cc ("More AP / SP bits for the 34K, the Malta bits and things."), that is Linux 2.6.15, and we can consider that a part of the Linux ABI. Mentioning emulation in the context of R2 is therefore misleading in my opinion and the change description needs to be rewritten. Maciej
On 04/12/2020 07:58, Maciej W. Rozycki wrote: > On Mon, 30 Nov 2020, Adhemerval Zanella via Libc-alpha wrote: > >>> MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be >>> enough for glibc. >>> >>> DO remember Linux/MIPS added emulation for 'rdhwr %0, $2',when disabled >>> or not supported, which would make the precision worse. If you got >>> unreasonable result, check your CPU Manual for whether your CPU >>> implemnted it or not >> >> It seems that rdhwr trap simulation has been on kernel since 2.6.15-rc1 >> (3c37026d43c47be), so it should be safe to assume current minimum kernel >> support for it. > > Nope, that was commit 1f5826bd0ed6c ("[MIPS] Added missing cases for > rdhwr emulation") and Linux 2.6.25 respectively. The other commit only > added User Local Register (ULR) access emulation for TLS pointer access. > > Also CP0 Counter (CC) register access emulation relies on `read_c0_count', > which is NOT universally supported, as not all MIPS CPUs have the CC, in > which case rubbish will be returned (the relevant instruction does not > trap on invalid CP0 register accesses). > > None of this seems to matter however if we only handle this for R2 and > higher ISA versions where both the CC and RDHWR are required by the > architecture. > >> However it does not only make the precision worse, but a missing rdwhr >> support would also slow down the loader since the hp-timing support is >> assumed to be 'fast' and loader code will use it regardless >> LD_DEBUG=statistics is set or not. It should be suffice to enabled it >> iff __mips_isa_rev is higher than 2, but do you know if there ARE chips >> which implement ISA higher than r2 that do not support this instruction? >> If so, how common are they? > > The RDHWR instruction is mandatory, though access to individual registers > is controlled by the kernel, via the CP0 HWREna register bitmask. We have > had access enabled to registers 3:0 (CC is $2) unconditionally however: > > if (cpu_has_mips_r2_r6) > hwrena |= MIPS_HWRENA_CPUNUM | > MIPS_HWRENA_SYNCISTEP | > MIPS_HWRENA_CC | > MIPS_HWRENA_CCRES; > > ever since commit e01402b115cc ("More AP / SP bits for the 34K, the Malta > bits and things."), that is Linux 2.6.15, and we can consider that a part > of the Linux ABI. Mentioning emulation in the context of R2 is therefore > misleading in my opinion and the change description needs to be rewritten. > > Maciej > Thanks for the thoroughly explanation, it answer my concerns about enabling hp-timing for MIPS R2.
diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h new file mode 100644 index 0000000000..128315d0bf --- /dev/null +++ b/sysdeps/mips/hp-timing.h @@ -0,0 +1,43 @@ +/* High precision, low overhead timing functions. MIPS version. + Copyright (C) 2002-2020 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _HP_TIMING_H +#define _HP_TIMING_H 1 + +#if __mips_isa_rev >= 2 +/* We always assume having the timestamp register. */ +#define HP_TIMING_AVAIL (0) +#define HP_SMALL_TIMING_AVAIL (1) + +/* We indeed have inlined functions. */ +#define HP_TIMING_INLINE (1) + +/* We use 32bit values for the times. */ +typedef unsigned int hp_timing_t; + +/* Read the cp0 count, this maybe inaccurate. */ +#define HP_TIMING_NOW(Var) \ + ({ unsigned int _count; \ + asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \ + (Var) = _count; }) + +#include <hp-timing-common.h> + +#endif + +#endif /* hp-timing.h */