From patchwork Thu Apr 2 16:29:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 38716 Return-Path: X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from esa4.hgst.iphmx.com (esa4.hgst.iphmx.com [216.71.154.42]) by sourceware.org (Postfix) with ESMTPS id 73F98388B803 for ; Thu, 2 Apr 2020 16:37:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 73F98388B803 IronPort-SDR: hcnVsOno2GLwVlNXUNbOSQdQbXQRfaTcwhk0deYMHPjuXTZaq+9Ou+61k8yuxigCU5zD24P5JQ 6AecPIcLsxKOVpu60zcGnHMnKSYcNf4Urpk4In7rFMooTPzRC4UUD110u1xlipSob8W4vPoC6w eq0ZZ35VVg7keoPldN5p2dP05Ey7Po/7B68pMPVF426X2tlicE/dg1B9s6xg/M+yuvvrKRcFf9 eoFtRJqGGwWEJ64kqgOqjgSBjpLiu5AmoDgCOkIol8M0j9ucFjmrEneBXlFvgp3wZoRV5enrli EQk= X-IronPort-AV: E=Sophos;i="5.72,336,1580745600"; d="scan'208";a="134426334" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 03 Apr 2020 00:37:27 +0800 IronPort-SDR: WgXCsEQX7avrdYmpRxTkKOagMdz3tJBxy88ccWE/54WGzS8VI1Sydf1RUy34rFvdzJSYs53ydm hp1Dam4C3jB3o9yKOWsB/ybmJcOY6PS3mFE/hnmDPFpjKkSZsxkRIOWCDMo5ObFhX0HVbM6tgO JAx44Rel9HNsexFw4n2tPmlw0WtMm4iwzAVE2R0HPuZF7V4YubmEWLTIU+H7QdJpYndvOpFTno zTnsj4e4B75VEEVt4Qsay0s8pVFPerDk0F8qs9NXqkwor7KK59qx6uUQScDNmeBfwgE/9+EE5A pwei9W0Td75xMUaWclV+Wzxg Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2020 09:28:18 -0700 IronPort-SDR: w09O2UWD3iSf2zMNyza2ctU/0WcN1AUiqPdsEwvNk1txBGke30bpMj+on30uXPNFOMDg9ftm+D 3fSRuZB6VuNM2kTAdN3iEL6qfarU6VCO9BRN4sP2/d9oZ4Hz+WeJzENam3c3PJyLswjKKa8VX4 y9cwVDV3qIabAx5er2Na0uLq4qcrHkFPD95/JUUbCsa/nE2Eb7JSwpGdP1yu3uPIFGdLwP1/j/ XTd10yhDRD3EH39V8N3oIdmQ78WnnFJ2SpCIxK3WnfUBwjz2+jyBQf/CaAneZ1pVpO/Ts48I4H qpw= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.43]) by uls-op-cesaip02.wdc.com with ESMTP; 02 Apr 2020 09:37:27 -0700 From: Alistair Francis To: libc-alpha@sourceware.org Cc: alistair23@gmail.com, Zong Li Subject: [PATCH 09/18] RISC-V: The ABI implementation for 32-bit Date: Thu, 2 Apr 2020 09:29:39 -0700 Message-Id: <20200402162939.358617-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200402162939.358617-1-alistair.francis@wdc.com> References: <20200402162939.358617-1-alistair.francis@wdc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-26.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Apr 2020 16:37:36 -0000 From: Zong Li This patch adds the ABI implementation about 32 bit version. It contains the Linux-specific and RISC-V architecture code, I've collected here. --- sysdeps/riscv/bits/wordsize.h | 4 +- sysdeps/riscv/nptl/bits/pthreadtypes-arch.h | 10 +++- sysdeps/riscv/nptl/bits/struct_rwlock.h | 27 +++++++++- sysdeps/riscv/sfp-machine.h | 27 +++++++++- sysdeps/riscv/sys/asm.h | 5 +- .../unix/sysv/linux/riscv/jmp_buf-macros.h | 53 +++++++++++++++++++ 6 files changed, 121 insertions(+), 5 deletions(-) create mode 100644 sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h diff --git a/sysdeps/riscv/bits/wordsize.h b/sysdeps/riscv/bits/wordsize.h index faccc71828..ee430d9036 100644 --- a/sysdeps/riscv/bits/wordsize.h +++ b/sysdeps/riscv/bits/wordsize.h @@ -25,5 +25,7 @@ #if __riscv_xlen == 64 # define __WORDSIZE_TIME64_COMPAT32 1 #else -# error "rv32i-based targets are not supported" +# define __WORDSIZE_TIME64_COMPAT32 0 +# define __WORDSIZE32_SIZE_ULONG 0 +# define __WORDSIZE32_PTRDIFF_LONG 0 #endif diff --git a/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h index c3c72d6c10..363034c38a 100644 --- a/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h +++ b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h @@ -32,7 +32,15 @@ # define __SIZEOF_PTHREAD_BARRIER_T 32 # define __SIZEOF_PTHREAD_BARRIERATTR_T 4 #else -# error "rv32i-based systems are not supported" +# define __SIZEOF_PTHREAD_ATTR_T 32 +# define __SIZEOF_PTHREAD_MUTEX_T 32 +# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 +# define __SIZEOF_PTHREAD_COND_T 48 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 48 +# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 +# define __SIZEOF_PTHREAD_BARRIER_T 20 +# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 #endif #define __LOCK_ALIGNMENT diff --git a/sysdeps/riscv/nptl/bits/struct_rwlock.h b/sysdeps/riscv/nptl/bits/struct_rwlock.h index acfaa75e1b..b478da0132 100644 --- a/sysdeps/riscv/nptl/bits/struct_rwlock.h +++ b/sysdeps/riscv/nptl/bits/struct_rwlock.h @@ -32,14 +32,39 @@ struct __pthread_rwlock_arch_t unsigned int __writers_futex; unsigned int __pad3; unsigned int __pad4; +#if __riscv_xlen == 64 int __cur_writer; int __shared; unsigned long int __pad1; unsigned long int __pad2; unsigned int __flags; +#else +# if __BYTE_ORDER == __BIG_ENDIAN + unsigned char __pad1; + unsigned char __pad2; + unsigned char __shared; + unsigned char __flags; +# else + unsigned char __flags; + unsigned char __shared; + unsigned char __pad1; + unsigned char __pad2; +# endif + int __cur_writer; +#endif }; -#define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ +#if __riscv_xlen == 64 +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, __flags +#else +# if __BYTE_ORDER == __BIG_ENDIAN +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, __flags, 0 +# else +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ + 0, 0, 0, 0, 0, 0, __flags, 0, 0, 0, 0 +# endif +#endif #endif diff --git a/sysdeps/riscv/sfp-machine.h b/sysdeps/riscv/sfp-machine.h index 08a84fd701..aef8c61a67 100644 --- a/sysdeps/riscv/sfp-machine.h +++ b/sysdeps/riscv/sfp-machine.h @@ -22,7 +22,32 @@ #if __riscv_xlen == 32 -# error "rv32i-based targets are not supported" +# define _FP_W_TYPE_SIZE 32 +# define _FP_W_TYPE unsigned long +# define _FP_WS_TYPE signed long +# define _FP_I_TYPE long + +# define _FP_MUL_MEAT_S(R, X, Y) \ + _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_D(R, X, Y) \ + _FP_MUL_MEAT_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_Q(R, X, Y) \ + _FP_MUL_MEAT_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +# define _FP_MUL_MEAT_DW_S(R, X, Y) \ + _FP_MUL_MEAT_DW_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_DW_D(R, X, Y) \ + _FP_MUL_MEAT_DW_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_DW_Q(R, X, Y) \ + _FP_MUL_MEAT_DW_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +# define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (S, R, X, Y) +# define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv (D, R, X, Y) +# define _FP_DIV_MEAT_Q(R, X, Y) _FP_DIV_MEAT_4_udiv (Q, R, X, Y) + +# define _FP_NANFRAC_S _FP_QNANBIT_S +# define _FP_NANFRAC_D _FP_QNANBIT_D, 0 +# define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0 #else diff --git a/sysdeps/riscv/sys/asm.h b/sysdeps/riscv/sys/asm.h index bd2de17e17..e314133ce4 100644 --- a/sysdeps/riscv/sys/asm.h +++ b/sysdeps/riscv/sys/asm.h @@ -26,7 +26,10 @@ # define REG_S sd # define REG_L ld #elif __riscv_xlen == 32 -# error "rv32i-based targets are not supported" +# define PTRLOG 2 +# define SZREG 4 +# define REG_S sw +# define REG_L lw #else # error __riscv_xlen must equal 32 or 64 #endif diff --git a/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h b/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h new file mode 100644 index 0000000000..7e48f24345 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h @@ -0,0 +1,53 @@ +/* jump buffer constants for RISC-V + Copyright (C) 2017-2020 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +/* Produced by this program: + + #include + #include + #include + #include + + int main (int argc, char **argv) + { + printf ("#define JMP_BUF_SIZE %d\n", sizeof (jmp_buf)); + printf ("#define JMP_BUF_ALIGN %d\n", __alignof__ (jmp_buf)); + printf ("#define SIGJMP_BUF_SIZE %d\n", sizeof (sigjmp_buf)); + printf ("#define SIGJMP_BUF_ALIGN %d\n", __alignof__ (sigjmp_buf)); + printf ("#define MASK_WAS_SAVED_OFFSET %d\n", offsetof (struct __jmp_buf_tag, __mask_was_saved)); + printf ("#define SAVED_MASK_OFFSET %d\n", offsetof (struct __jmp_buf_tag, __saved_mask)); + } */ + +#if defined __riscv_float_abi_soft +# define JMP_BUF_SIZE 188 +# define JMP_BUF_ALIGN 4 +# define SIGJMP_BUF_SIZE 188 +# define SIGJMP_BUF_ALIGN 4 +# define MASK_WAS_SAVED_OFFSET 56 +# define SAVED_MASK_OFFSET 60 +#elif defined __riscv_float_abi_double +# define JMP_BUF_SIZE 288 +# define JMP_BUF_ALIGN 8 +# define SIGJMP_BUF_SIZE 288 +# define SIGJMP_BUF_ALIGN 8 +# define MASK_WAS_SAVED_OFFSET 152 +# define SAVED_MASK_OFFSET 156 +#else +# error "Unknown RISC-V floating-point ABI" +#endif