diff mbox series

[1/3] x86: Refactor platform support in cpu_features

Message ID 20200317044646.29707-2-PMallappa@amd.com
State New
Headers show
Series RFC: Platform Support for AMD Zen and AVX2/AVX | expand

Commit Message

Prem Mallappa March 17, 2020, 4:46 a.m. UTC
From: Prem Mallappa <Premachandra.Mallappa@amd.com>

This is a preliminary support to have platform
for AMD processors.

Signed-off-by: Prem Mallappa <Premachandra.Mallappa@amd.com>
---
 sysdeps/x86/cpu-features.c | 99 ++++++++++++++++++++------------------
 1 file changed, 53 insertions(+), 46 deletions(-)
diff mbox series

Patch

diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 81a170a819..a36f385976 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -302,6 +302,58 @@  _Static_assert (((index_arch_Fast_Unaligned_Load
 		     == index_arch_Fast_Copy_Backward)),
 		"Incorrect index_arch_Fast_Unaligned_Load");
 
+static void
+set_platform (struct cpu_features *cpu_features)
+{
+#ifdef __x86_64__
+  const char *platform = NULL;
+
+  GLRO(dl_hwcap) = HWCAP_X86_64;
+
+  if (cpu_features->basic.kind == arch_kind_intel)
+    {
+      if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
+	  && CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
+	{
+	  if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
+	    {
+	      if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
+		platform = "xeon_phi";
+	    }
+	  else
+	    {
+	      if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW)
+		  && CPU_FEATURES_CPU_P (cpu_features, AVX512DQ)
+		  && CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
+		GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1;
+	    }
+	}
+
+      if (platform == NULL
+	  && CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable)
+	  && CPU_FEATURES_ARCH_P (cpu_features, FMA_Usable)
+	  && CPU_FEATURES_CPU_P (cpu_features, BMI1)
+	  && CPU_FEATURES_CPU_P (cpu_features, BMI2)
+	  && CPU_FEATURES_CPU_P (cpu_features, LZCNT)
+	  && CPU_FEATURES_CPU_P (cpu_features, MOVBE)
+	  && CPU_FEATURES_CPU_P (cpu_features, POPCNT))
+	platform = "haswell";
+    }
+
+  if (platform != NULL)
+    GLRO(dl_platform) = platform;
+#else
+  GLRO(dl_hwcap) = 0;
+  if (CPU_FEATURES_CPU_P (cpu_features, SSE2))
+    GLRO(dl_hwcap) |= HWCAP_X86_SSE2;
+
+  if (CPU_FEATURES_ARCH_P (cpu_features, I686))
+    GLRO(dl_platform) = "i686";
+  else if (CPU_FEATURES_ARCH_P (cpu_features, I586))
+    GLRO(dl_platform) = "i586";
+#endif
+}
+
 static inline void
 init_cpu_features (struct cpu_features *cpu_features)
 {
@@ -506,52 +558,7 @@  no_cpuid:
   GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT;
 #endif
 
-#ifdef __x86_64__
-  GLRO(dl_hwcap) = HWCAP_X86_64;
-  if (cpu_features->basic.kind == arch_kind_intel)
-    {
-      const char *platform = NULL;
-
-      if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
-	  && CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
-	{
-	  if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
-	    {
-	      if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
-		platform = "xeon_phi";
-	    }
-	  else
-	    {
-	      if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW)
-		  && CPU_FEATURES_CPU_P (cpu_features, AVX512DQ)
-		  && CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
-		GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1;
-	    }
-	}
-
-      if (platform == NULL
-	  && CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable)
-	  && CPU_FEATURES_ARCH_P (cpu_features, FMA_Usable)
-	  && CPU_FEATURES_CPU_P (cpu_features, BMI1)
-	  && CPU_FEATURES_CPU_P (cpu_features, BMI2)
-	  && CPU_FEATURES_CPU_P (cpu_features, LZCNT)
-	  && CPU_FEATURES_CPU_P (cpu_features, MOVBE)
-	  && CPU_FEATURES_CPU_P (cpu_features, POPCNT))
-	platform = "haswell";
-
-      if (platform != NULL)
-	GLRO(dl_platform) = platform;
-    }
-#else
-  GLRO(dl_hwcap) = 0;
-  if (CPU_FEATURES_CPU_P (cpu_features, SSE2))
-    GLRO(dl_hwcap) |= HWCAP_X86_SSE2;
-
-  if (CPU_FEATURES_ARCH_P (cpu_features, I686))
-    GLRO(dl_platform) = "i686";
-  else if (CPU_FEATURES_ARCH_P (cpu_features, I586))
-    GLRO(dl_platform) = "i586";
-#endif
+  set_platform(cpu_features);
 
 #if CET_ENABLED
 # if HAVE_TUNABLES