From patchwork Wed Aug 1 15:20:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 28716 Received: (qmail 96590 invoked by alias); 1 Aug 2018 15:20:53 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 96569 invoked by uid 89); 1 Aug 2018 15:20:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy= X-HELO: mga17.intel.com From: "H.J. Lu" To: libc-alpha@sourceware.org Subject: [PATCH] x86: Move STATE_SAVE_OFFSET/STATE_SAVE_MASK to sysdep.h Date: Wed, 1 Aug 2018 08:20:50 -0700 Message-Id: <20180801152050.18135-1-hjl.tools@gmail.com> Move STATE_SAVE_OFFSET and STATE_SAVE_MASK to sysdep.h to make sysdeps/x86/cpu-features.h a C header file. * sysdeps/x86/cpu-features.h (STATE_SAVE_OFFSET): Removed. (STATE_SAVE_MASK): Likewise. Don't check __ASSEMBLER__ to include . * sysdeps/x86/sysdep.h (STATE_SAVE_OFFSET): New. (STATE_SAVE_MASK): Likewise. * sysdeps/x86_64/dl-trampoline.S: Include instead of . --- sysdeps/x86/cpu-features.h | 14 -------------- sysdeps/x86/sysdep.h | 9 +++++++++ sysdeps/x86_64/dl-trampoline.S | 2 +- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 347a4b118d..5fd20d8cb6 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -92,18 +92,6 @@ /* The current maximum size of the feature integer bit array. */ #define FEATURE_INDEX_MAX 1 -/* Offset for fxsave/xsave area used by _dl_runtime_resolve. Also need - space to preserve RCX, RDX, RSI, RDI, R8, R9 and RAX. It must be - aligned to 16 bytes for fxsave and 64 bytes for xsave. */ -#define STATE_SAVE_OFFSET (8 * 7 + 8) - -/* Save SSE, AVX, AVX512, mask and bound registers. */ -#define STATE_SAVE_MASK \ - ((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7)) - -#ifdef __ASSEMBLER__ -# include -#else /* __ASSEMBLER__ */ enum { COMMON_CPUID_INDEX_1 = 0, @@ -267,8 +255,6 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_arch_XSAVEC_Usable FEATURE_INDEX_1 # define index_arch_Prefer_FSRM FEATURE_INDEX_1 -#endif /* !__ASSEMBLER__ */ - #ifdef __x86_64__ # define HAS_CPUID 1 #elif defined __i586__ || defined __pentium__ diff --git a/sysdeps/x86/sysdep.h b/sysdeps/x86/sysdep.h index 8776ad8374..f41f4ebd42 100644 --- a/sysdeps/x86/sysdep.h +++ b/sysdeps/x86/sysdep.h @@ -48,6 +48,15 @@ enum cf_protection_level # define SHSTK_ENABLED 0 #endif +/* Offset for fxsave/xsave area used by _dl_runtime_resolve. Also need + space to preserve RCX, RDX, RSI, RDI, R8, R9 and RAX. It must be + aligned to 16 bytes for fxsave and 64 bytes for xsave. */ +#define STATE_SAVE_OFFSET (8 * 7 + 8) + +/* Save SSE, AVX, AVX512, mask and bound registers. */ +#define STATE_SAVE_MASK \ + ((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7)) + #ifdef __ASSEMBLER__ /* Syntactic details of assembler. */ diff --git a/sysdeps/x86_64/dl-trampoline.S b/sysdeps/x86_64/dl-trampoline.S index ef1425cbb9..fd918510fe 100644 --- a/sysdeps/x86_64/dl-trampoline.S +++ b/sysdeps/x86_64/dl-trampoline.S @@ -18,7 +18,7 @@ #include #include -#include +#include #include #ifndef DL_STACK_ALIGNMENT