From patchwork Fri Jan 26 05:44:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 25551 Received: (qmail 5956 invoked by alias); 26 Jan 2018 05:45:04 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 5704 invoked by uid 89); 26 Jan 2018 05:45:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg0-f67.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=Nfh0lOfiQ0DgXNEq7JP9IS1CsXMNlyWuYYvHA8id6/U=; b=SumG9y/FubL2K12jDfvV6+XRKybClCnyhMc5AK1eboBr8e92bBIJYAuFIu/6UW4IOI 3BrDM4UvxvqAAGQe1H//QB/3X4TzsFL+kg4jBsW9zZGdzDPrizcV3ODIzVdrGRApk+Qm kbsMovGCucQHNk2l9xeWFkEHKcjm96GOIQfpNBw/vjNx6YDDsxEalAagp1hjEknTphT6 /JAQDos//0ZAAsJq6mrxcEyNkijxOmtwf0gzWOgqgpwDxYFuzdEmH/ZpNrDZ0kNJDC7X ZNoG+x/myHqzrEWRom2j2qdFDQtSBnsVltRCx4d8CzqgKNfUwMGSZuHivVmp6hAHa/wO qFmQ== X-Gm-Message-State: AKwxytc2RAZIocy1rs2J9oReZuZcpb2sG9bN7a791anK/BZsKgSRZAIb 037kdTXyH4JCCDEWQHpXY+Mw09bnKLY= X-Google-Smtp-Source: AH8x224MQIYQ9Dp1aKSHME1wXGGg3fm7d4EHYbgiN0p+JpQtjy7czX1d0d+5H6BJqnbxZgwBmM8mOQ== X-Received: by 2002:a17:902:d917:: with SMTP id c23-v6mr13792151plz.231.1516945499268; Thu, 25 Jan 2018 21:44:59 -0800 (PST) Subject: [PATCH v6 04/16] Add documentation for __riscv_flush_icache Date: Thu, 25 Jan 2018 21:44:31 -0800 Message-Id: <20180126054443.22702-5-palmer@dabbelt.com> In-Reply-To: <20180126054443.22702-1-palmer@dabbelt.com> References: <20180126054443.22702-1-palmer@dabbelt.com> Cc: patches@groups.riscv.org, Andrew Waterman , dj@redhat.com, Darius Rad , Palmer Dabbelt From: Palmer Dabbelt To: libc-alpha@sourceware.org, joseph@codesourcery.com This function is used by GCC to enforce ordering between data writes and instruction fetches, and while we'd prefer that users rely on the GCC intrinsic when possible this is user visible in case that's not possible. 2018-01-13 Palmer Dabbelt * manual/platform.texi: Add RISC-V documenation for __riscv_flush_icache. --- manual/platform.texi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/manual/platform.texi b/manual/platform.texi index cb166641fb71..b8721a071272 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -6,6 +6,7 @@ @menu * PowerPC:: Facilities Specific to the PowerPC Architecture +* RISC-V:: Facilities Specific to the RISC-V Architecture @end menu @node PowerPC @@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time interval expires or if an attempt is made to set the priority to medium high when it is not allowed, the priority is set to medium. @end deftypefun + +@node RISC-V +@appendixsec RISC-V-specific Facilities + +Cache management facilities specific to RISC-V systems that implement the Linux +ABI are declared in @file{sys/cachectl.h}. + +@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags}) +@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} +Enforce ordering between stores and instruction cache fetches. The range of +addresses over which ordering is enforced is specified by @var{start} and +@var{end}. The @var{flags} argument controls the extent of this ordering, with +the default behavior (a @var{flags} value of 0) being to enforce the fence on +all threads in the current process. Setting the +@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing +ordering on only the current thread is necessary. All other flag bits are +reserved. +@end deftypefun