From patchwork Thu Jan 25 04:36:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 25513 Received: (qmail 19267 invoked by alias); 25 Jan 2018 04:36:43 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 19170 invoked by uid 89); 25 Jan 2018 04:36:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=expires X-HELO: mail-pg0-f50.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=s3iSyrBEU2FtkUtih6RAPvPkGctINM/hcno1sAmHYJ0=; b=JIpVePhYoflkGuZK92o6n0ZRnaeIQ6ZsHyFRqi2otcJBmrN5dQPuL7LI6+Qu4bFYk5 O/H0v3WPCIYwTjRYWXDzIHC6uAy5jE+oGnW1QDIIy0Ex8TiAkaFwoWPVd6Zxhi1dxHrE LIUMsP/73m4ahmGwUhpFOZL/dlCvDPLwV4VrFqyEvTW+lwgE+ljmIOV70IKMRSNjek+j ivI0SOoNZ5KOwadG1bFxO3TGQLYWOEJv6oyY1vvbXA5hFiGDs6QBHaRBvd6LGjZHZQ02 WE3PgdNrjEJyRMVdiZ6747nfGezLn5551U1PKUM9UBTVXEA4R7J+p/9mhXLaOX8/QIUq d1zA== X-Gm-Message-State: AKwxyteCIH8Pa6u+g8N08FMBqgOCdJBZJUZr5kjwshmufgHLgHQG8vnZ XSR543caVB+7IDFkBFyxNQ2JAQ== X-Google-Smtp-Source: AH8x2261n4FCgGWx9D/1zfsaBYD+zMDWmrN1QcFe3UQstI1vg85EfcJgllcmt3PM68pKBu9sFoAvQA== X-Received: by 2002:a17:902:7614:: with SMTP id k20-v6mr10130077pll.343.1516854999180; Wed, 24 Jan 2018 20:36:39 -0800 (PST) Subject: [PATCH 04/17] Add documentation for __riscv_flush_icache Date: Wed, 24 Jan 2018 20:36:08 -0800 Message-Id: <20180125043621.19972-5-palmer@dabbelt.com> In-Reply-To: <20180125043621.19972-1-palmer@dabbelt.com> References: <20180125043621.19972-1-palmer@dabbelt.com> Cc: Andrew Waterman , Darius Rad , dj@redhat.com, patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: libc-alpha@sourceware.org, joseph@codesourcery.com I don't know if this is actually the right place to put this: it's a Linux-specific function, and while users can call it we'd really prefer they use rely on GCC to emit it when necessary from via its cache flushing intrinsics. 2018-01-13 Palmer Dabbelt * manual/platform.texi: Add RISC-V documenation for __riscv_flush_icache. --- manual/platform.texi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/manual/platform.texi b/manual/platform.texi index cb166641fb71..b8721a071272 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -6,6 +6,7 @@ @menu * PowerPC:: Facilities Specific to the PowerPC Architecture +* RISC-V:: Facilities Specific to the RISC-V Architecture @end menu @node PowerPC @@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time interval expires or if an attempt is made to set the priority to medium high when it is not allowed, the priority is set to medium. @end deftypefun + +@node RISC-V +@appendixsec RISC-V-specific Facilities + +Cache management facilities specific to RISC-V systems that implement the Linux +ABI are declared in @file{sys/cachectl.h}. + +@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags}) +@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} +Enforce ordering between stores and instruction cache fetches. The range of +addresses over which ordering is enforced is specified by @var{start} and +@var{end}. The @var{flags} argument controls the extent of this ordering, with +the default behavior (a @var{flags} value of 0) being to enforce the fence on +all threads in the current process. Setting the +@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing +ordering on only the current thread is necessary. All other flag bits are +reserved. +@end deftypefun