From patchwork Tue Aug 8 19:24:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lu, Hongjiu" X-Patchwork-Id: 21998 Received: (qmail 126647 invoked by alias); 8 Aug 2017 19:25:36 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 126410 invoked by uid 89); 8 Aug 2017 19:25:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: mga07.intel.com X-ExtLoop1: 1 Date: Tue, 8 Aug 2017 12:24:54 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] x86: Add IBT/SHSTK bits to cpu-features Message-ID: <20170808192454.GA32301@gmail.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.8.3 (2017-05-23) Add IBT/SHSTK bits to cpu-features for Shadow Stack in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Any comments or objections? H.J. --- * sysdeps/x86/cpu-features.h (bit_cpu_BIT): New. (bit_cpu_SHSTK): Likewise. (index_cpu_IBT): Likewise. (index_cpu_SHSTK): Likewise. (reg_IBT): Likewise. (reg_SHSTK): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Handle index_cpu_IBT and index_cpu_SHSTK. --- sysdeps/x86/cpu-features.h | 8 ++++++++ sysdeps/x86/cpu-tunables.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index af52689123..9733e6ee66 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -74,6 +74,8 @@ #define bit_cpu_AVX512CD (1 << 28) #define bit_cpu_AVX512BW (1 << 30) #define bit_cpu_AVX512VL (1u << 31) +#define bit_cpu_IBT (1u << 20) +#define bit_cpu_SHSTK (1u << 7) /* XCR0 Feature flags. */ #define bit_XMM_state (1 << 1) @@ -103,6 +105,8 @@ # define index_cpu_AVX2 COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET # define index_cpu_ERMS COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET # define index_cpu_MOVBE COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET +# define index_cpu_IBT COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EDX_OFFSET +# define index_cpu_SHSTK COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_ECX_OFFSET # define index_arch_Fast_Rep_String FEATURE_INDEX_1*FEATURE_SIZE # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1*FEATURE_SIZE @@ -220,6 +224,8 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_cpu_LZCNT COMMON_CPUID_INDEX_1 # define index_cpu_MOVBE COMMON_CPUID_INDEX_1 # define index_cpu_POPCNT COMMON_CPUID_INDEX_1 +# define index_cpu_IBT COMMON_CPUID_INDEX_7 +# define index_cpu_SHSTK COMMON_CPUID_INDEX_7 # define reg_CX8 edx # define reg_CMOV edx @@ -249,6 +255,8 @@ extern const struct cpu_features *__get_cpu_features (void) # define reg_LZCNT ecx # define reg_MOVBE ecx # define reg_POPCNT ecx +# define reg_IBT edx +# define reg_SHSTK ecx # define index_arch_Fast_Rep_String FEATURE_INDEX_1 # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1 diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c index 872dd1267f..0ab708cca8 100644 --- a/sysdeps/x86/cpu-tunables.c +++ b/sysdeps/x86/cpu-tunables.c @@ -164,6 +164,7 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, CX8, 3); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, FMA, 3); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, HTT, 3); + CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, IBT, 3); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, RTM, 3); } break; @@ -186,6 +187,7 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) { CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, LZCNT, 5); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, MOVBE, 5); + CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SHSTK, 5); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSSE3, 5); } break;