From patchwork Wed May 24 03:29:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 20556 Received: (qmail 45096 invoked by alias); 24 May 2017 03:29:19 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 45084 invoked by uid 89); 24 May 2017 03:29:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2534, family X-HELO: mail-oi0-f43.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:mime-version :content-disposition:user-agent; bh=CtFQhCtgKWPRES0vo1EFwqZlQl9QHe4KgbUkOkJ2rpM=; b=LLY2wCztElPXUTVGtA9KQMc4csW9Atpf9vm0PFySHSVEUyMTXCv9WQa9+tJK00XN2S BEyCMEi5PcPjXCptFHt0fNz9nx3EQDs7nMqkNopGmz2mQ+7dRZhPkZWE+sL04Gl8+C37 E7cYukWHKz8YFyyHiadDjVIq0JhWZk+LT5s/hR4nHObSyAYKjxXB8R5sj0BSprXxB0Q8 6iaRF98hSmsl3lBCMPl3xoTknaiCE1XsrKpC64Qleo8994YfS82W2J7hbsaBhU3aEcmx JqXD7CK/Je4pw4k7scoETDI8SyF4YgXAkqMiTt+NlAKTNUJ+KuBQsFZhDKLyR+AAHqVx jjKA== X-Gm-Message-State: AODbwcARc3ZxLjrl7eEczRY+udX/NUSEKNT86ynYUoMOidV6YOZo+HHt eqExbtKIeMSHf9rJ X-Received: by 10.202.55.193 with SMTP id e184mr12869958oia.125.1495596559571; Tue, 23 May 2017 20:29:19 -0700 (PDT) Date: Tue, 23 May 2017 20:29:17 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] x86: Add cache info to cpu_features Message-ID: <20170524032917.GA18498@gmail.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.8.0 (2017-02-23) This patch adds cache info to cpu_features to support tunables for both cache info as well as CPU features in a single x86 namespace. Since init_cacheinfo is in libc.so and cpu_features is in ld.so, cache info and CPU features must be in a place for tunables. Any comments? H.J. --- * sysdeps/x86/cacheinfo.c (init_cacheinfo): Use data_size, shared_size and non_temporal_threshold from cpu_features if they aren't not zero. * sysdeps/x86/cpu-features.h (cache_info): New. (cpu_features): Add cache. --- sysdeps/x86/cacheinfo.c | 11 ++++++++++- sysdeps/x86/cpu-features.h | 13 +++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 12ffeef..321fbb6 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -745,6 +745,9 @@ intel_bug_no_cache_info: #endif } + if (cpu_features->cache.data_size != 0) + data = cpu_features->cache.data_size; + if (data > 0) { __x86_raw_data_cache_size_half = data / 2; @@ -755,6 +758,9 @@ intel_bug_no_cache_info: __x86_data_cache_size = data; } + if (cpu_features->cache.shared_size != 0) + shared = cpu_features->cache.shared_size; + if (shared > 0) { __x86_raw_shared_cache_size_half = shared / 2; @@ -768,7 +774,10 @@ intel_bug_no_cache_info: /* The large memcpy micro benchmark in glibc shows that 6 times of shared cache size is the approximate value above which non-temporal store becomes faster. */ - __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6; + __x86_shared_non_temporal_threshold + = (cpu_features->cache.non_temporal_threshold != 0 + ? cpu_features->cache.non_temporal_threshold + : __x86_shared_cache_size * 6); } #endif diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 31c7c80..f428dca 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -185,6 +185,18 @@ #else /* __ASSEMBLER__ */ +struct cache_info +{ + /* Data cache size for use in memory and string routines, typically + L1 size. */ + long int data_size; + /* Shared cache size for use in memory and string routines, typically + L2 or L3 size. */ + long int shared_size; + /* Threshold to use non temporal store. */ + long int non_temporal_threshold; +}; + enum { COMMON_CPUID_INDEX_1 = 0, @@ -214,6 +226,7 @@ struct cpu_features unsigned int family; unsigned int model; unsigned int feature[FEATURE_INDEX_MAX]; + struct cache_info cache; }; /* Used from outside of glibc to get access to the CPU features