From patchwork Sun Feb 12 23:22:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Blanchard X-Patchwork-Id: 19237 Received: (qmail 98207 invoked by alias); 12 Feb 2017 23:22:32 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 98186 invoked by uid 89); 12 Feb 2017 23:22:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL, BAYES_05, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=uintmax_t, sk:atomic, 2307, Hx-languages-length:1389 X-HELO: hr2.samba.org Date: Mon, 13 Feb 2017 10:22:20 +1100 From: Anton Blanchard To: tuliom@linux.vnet.ibm.com, cseo@linux.vnet.ibm.com Cc: libc-alpha@sourceware.org Subject: [PATCH] powerpc: Use lwsync on 64bit Message-ID: <20170213102220.31ba7d56@kryten> MIME-Version: 1.0 Either an isync or an lwsync can be used as an acquire barrier after a larx/stcx/bne sequence. All 64bit CPUs support lwsync and since the isync instruction has other side effects that we don't need, use lwsync. 2017-02-12 Anton Blanchard * sysdeps/powerpc/atomic-machine.h: Allow __ARCH_ACQ_INSTR to be overridden. * sysdeps/powerpc/powerpc64/atomic-machine.h: define __ARCH_ACQ_INSTR diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h index 0a58203..31d67fa 100644 --- a/sysdeps/powerpc/atomic-machine.h +++ b/sysdeps/powerpc/atomic-machine.h @@ -57,7 +57,9 @@ typedef uintmax_t uatomic_max_t; # define __ARCH_ACQ_INSTR "" # define __ARCH_REL_INSTR "" #else -# define __ARCH_ACQ_INSTR "isync" +# ifndef __ARCH_ACQ_INSTR +# define __ARCH_ACQ_INSTR "isync" +# endif # ifndef __ARCH_REL_INSTR # define __ARCH_REL_INSTR "sync" # endif diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h index 40c308e..76c586a 100644 --- a/sysdeps/powerpc/powerpc64/atomic-machine.h +++ b/sysdeps/powerpc/powerpc64/atomic-machine.h @@ -230,6 +230,7 @@ * "light weight" sync can also be used for the release barrier. */ #ifndef UP +# define __ARCH_ACQ_INSTR "lwsync" # define __ARCH_REL_INSTR "lwsync" #endif #define atomic_write_barrier() __asm ("lwsync" ::: "memory")