diff mbox

Remove special L2 cache case for Knights Landing

Message ID 20160520214529.GA17587@intel.com
State Committed
Headers

Commit Message

Lu, Hongjiu May 20, 2016, 9:45 p.m. UTC 
  L2 cache is shared by 2 cores on Knights Landing, which has 4 threads
per core:

https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing

So L2 cache is shared by 8 threads on Knights Landing as reported by
CPUID.  We should remove special L2 cache case for Knights Landing.

I will check it in shortly.


H.J.
---
	[BZ #18185]
	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads
	sharing L2 cache to 2 for Knights Landing.
---
 ChangeLog               | 6 ++++++
 sysdeps/x86/cacheinfo.c | 2 --
 2 files changed, 6 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 020d3fd..182426b 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -573,8 +573,6 @@  init_cacheinfo (void)
 		{
 		  switch (model)
 		    {
-		    case 0x57:
-		      /* Knights Landing has L2 cache shared by 2 cores.  */
 		    case 0x37:
 		    case 0x4a:
 		    case 0x4d: