diff mbox

[committed,BZ,#20119] Correct Intel processor level type mask from CPUID

Message ID 20160519170617.GA10580@intel.com
State Committed
Headers

Commit Message

Lu, Hongjiu May 19, 2016, 5:06 p.m. UTC 
  Intel CPUID with EAX == 11 returns:

ECX Bits 07 - 00: Level number. Same value in ECX input.
    Bits 15 - 08: Level type.
    ^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
    Bits 31 - 16: Reserved.

Intel processor level type mask should be 0xff00, not 0xff0.

Tested on x86.  Checked in.

	[BZ #20119]
	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
	processor level type mask for CPUID with EAX == 11.
---
 ChangeLog               | 6 ++++++
 sysdeps/x86/cacheinfo.c | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/ChangeLog b/ChangeLog
index 8adf828..7ba904d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,11 @@ 
 2016-05-19  H.J. Lu  <hongjiu.lu@intel.com>
 
+	[BZ #20119]
+	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
+	processor level type mask for CPUID with EAX == 11.
+
+2016-05-19  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
 	logical threads if the HTT bit is 0.
 	* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 1f46d9d..020d3fd 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -552,7 +552,7 @@  init_cacheinfo (void)
 		      __cpuid_count (11, i++, eax, ebx, ecx, edx);
 
 		      int shipped = ebx & 0xff;
-		      int type = ecx & 0xff0;
+		      int type = ecx & 0xff00;
 		      if (shipped == 0 || type == 0)
 			break;
 		      else if (type == 0x200)