From patchwork Mon Mar 28 20:48:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lu, Hongjiu" X-Patchwork-Id: 11541 Received: (qmail 35306 invoked by alias); 28 Mar 2016 20:48:36 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 35235 invoked by uid 89); 28 Mar 2016 20:48:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.7 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=erms, movsb, REP, MOVSB X-HELO: mga04.intel.com X-ExtLoop1: 1 Date: Mon, 28 Mar 2016 13:48:30 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] Initial Enhanced REP MOVSB/STOSB (ERMS) support Message-ID: <20160328204830.GA402@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) The newer Intel processors support Enhanced REP MOVSB/STOSB (ERMS) which has a feature bit in CPUID. This patch adds the Enhanced REP MOVSB/STOSB (ERMS) bit to x86 cpu-features. I will use this in followup patches to optimize memcpy/memset with ERMS. Any comments? H.J. * sysdeps/x86/cpu-features.h (bit_cpu_ERMS): New. (index_cpu_ERMS): Likewise. (reg_ERMS): Likewise. --- sysdeps/x86/cpu-features.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index bfe1f4c..8f946c4 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -53,6 +53,7 @@ #define bit_cpu_FMA4 (1 << 16) /* COMMON_CPUID_INDEX_7. */ +#define bit_cpu_ERMS (1 << 9) #define bit_cpu_RTM (1 << 11) #define bit_cpu_AVX2 (1 << 5) #define bit_cpu_AVX512F (1 << 16) @@ -84,6 +85,7 @@ # define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET # define index_cpu_AVX COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET # define index_cpu_AVX2 COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET +# define index_cpu_ERMS COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET # define index_arch_Fast_Rep_String FEATURE_INDEX_1*FEATURE_SIZE # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1*FEATURE_SIZE @@ -228,6 +230,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_cpu_AVX2 COMMON_CPUID_INDEX_7 # define index_cpu_AVX512F COMMON_CPUID_INDEX_7 # define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7 +# define index_cpu_ERMS COMMON_CPUID_INDEX_7 # define index_cpu_RTM COMMON_CPUID_INDEX_7 # define index_cpu_FMA COMMON_CPUID_INDEX_1 # define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001 @@ -244,6 +247,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define reg_AVX2 ebx # define reg_AVX512F ebx # define reg_AVX512DQ ebx +# define reg_ERMS ebx # define reg_RTM ebx # define reg_FMA ecx # define reg_FMA4 ecx