diff mbox

BZ #18185: Wrong processor count for L2 cache sharing on Silvermont and Knights Landing

Message ID 20150331162648.GA26418@lucon.org
State Committed
Headers show

Commit Message

H.J. Lu March 31, 2015, 4:26 p.m. UTC
Hi,

Silvermont and Knights Landing have a modular system design with two cores
sharing an L2 cache.  If more than 2 cores are detected to shared L2 cache,
it should be adjusted for Silvermont and Knights Landing.

I am planning to check it in shortly.

H.J.
---
	[BZ #18185]
	* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
	sharing L2 cache to 2 for Silvermont/Knights Landing.
---
 sysdeps/x86_64/cacheinfo.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Ondrej Bilka April 3, 2015, 2:06 p.m. UTC | #1
On Tue, Mar 31, 2015 at 09:26:48AM -0700, H.J. Lu wrote:
> Hi,
> 
> Silvermont and Knights Landing have a modular system design with two cores
> sharing an L2 cache.  If more than 2 cores are detected to shared L2 cache,
> it should be adjusted for Silvermont and Knights Landing.
> 
> I am planning to check it in shortly.
> 
ok for me.
diff mbox

Patch

diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index f1cbf50..b99fb9a 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -585,6 +585,10 @@  init_cacheinfo (void)
       __cpuid (1, eax, ebx_1, ecx, edx);
 #endif
 
+      unsigned int family = (eax >> 8) & 0x0f;
+      unsigned int model = (eax >> 4) & 0x0f;
+      unsigned int extended_model = (eax >> 12) & 0xf0;
+
 #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
       /* Intel prefers SSSE3 instructions for memory/string routines
 	 if they are available.  */
@@ -647,6 +651,25 @@  init_cacheinfo (void)
 		}
 	    }
 	  threads += 1;
+	  if (threads > 2 && level == 2 && family == 6)
+	    {
+	      model += extended_model;
+	      switch (model)
+		{
+		case 0x57:
+		  /* Knights Landing has L2 cache shared by 2 cores.  */
+		case 0x37:
+		case 0x4a:
+		case 0x4d:
+		case 0x5a:
+		case 0x5d:
+		  /* Silvermont has L2 cache shared by 2 cores.  */
+		  threads = 2;
+		  break;
+		default:
+		  break;
+		}
+	    }
 	}
       else
 	{