From patchwork Mon Jan 14 14:49:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rogerio Alves X-Patchwork-Id: 31052 X-Patchwork-Delegate: tuliom@linux.vnet.ibm.com Received: (qmail 81828 invoked by alias); 14 Jan 2019 14:50:09 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 81455 invoked by uid 89); 14 Jan 2019 14:50:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, KHOP_DYNAMIC, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=POWER, reviews, H*Ad:D*ibm.com X-HELO: mx0a-001b2d01.pphosted.com To: libc-alpha@sourceware.org, Tulio Magno Quites Machado Filho From: Rogerio Alves Subject: [PATCH] powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6 Date: Mon, 14 Jan 2019 12:49:59 -0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 x-cbid: 19011414-0012-0000-0000-000016F9C85D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010404; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000274; SDB=6.01146382; UDB=6.00597066; IPR=6.00926668; MB=3.00025121; MTD=3.00000008; XFM=3.00000015; UTC=2019-01-14 14:50:04 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19011414-0013-0000-0000-000055D0A831 Message-Id: <1b571876-2d6e-312f-08b2-a4c58aadb504@linux.ibm.com> Hi, I've sent a patch https://sourceware.org/ml/libc-alpha/2018-11/msg00357.html that fix VSCR reading from ucontext_t for powerpc BZ#24088. The problem is that the test was fail to compile on POWER 5 and 6. The test was using __vector __int128_t and generating an error impossible register constraint in 'asm' if compiled without -mvsx flag. In fact the test doesn't need to use a __int128_t. A unsigned int should be fine. So I am sent another patch to fix this since the other patch was already committed. I will appreciate any comments or reviews on this. Regards, Rogerio From 1a70e67a2fda78bb56c34a882f85653e66bc087d Mon Sep 17 00:00:00 2001 From: Rogerio Alves Date: Mon, 14 Jan 2019 07:53:50 -0600 Subject: [PATCH] powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6. An error: impossible register constraint in 'asm' was raised on POWER 5 and 6 due a __vector __int128_t being used as operands without passing the option -msvx to gcc. However, the test doesn't need to use a __int128_t a unsigned int should work. 2019-01-14 Rogerio A. Cardoso * sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: Changed __vector __int128_t to vector unsigned int. --- sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c index 2dcf5bb..dbe06c8 100644 --- a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c +++ b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c @@ -44,8 +44,8 @@ do_test (void) uint32_t* vscr_ptr = vscr; uint32_t vscr_word; ucontext_t ucp; - __vector __int128_t v0 = {0}; - __vector __int128_t v1 = {0}; + __vector unsigned int v0 = {0}; + __vector unsigned int v1 = {0}; /* Set SAT bit in VSCR register. */ asm volatile (".machine push;\n" -- 2.7.4