diff mbox

powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6

Message ID 1b571876-2d6e-312f-08b2-a4c58aadb504@linux.ibm.com
State Committed
Delegated to: Tulio Magno Quites Machado Filho
Headers

Commit Message

Rogerio Alves Jan. 14, 2019, 2:49 p.m. UTC 
  Hi,

I've sent a patch 
https://sourceware.org/ml/libc-alpha/2018-11/msg00357.html that fix VSCR 
reading from ucontext_t for powerpc BZ#24088. The problem is that the 
test was fail to compile on POWER 5 and 6. The test was using __vector 
__int128_t and generating an error impossible register constraint in 
'asm' if compiled without -mvsx flag.

In fact the test doesn't need to use a __int128_t. A unsigned int should 
be fine. So I am sent another patch to fix this since the other patch 
was already committed. I will appreciate any comments or reviews on this.

Regards,
Rogerio

Comments

Tulio Magno Quites Machado Filho Jan. 15, 2019, 6:28 p.m. UTC | #1 
Rogerio Alves <rcardoso@linux.ibm.com> writes:

> Subject: [PATCH] powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6.
>
> An error: impossible register constraint in 'asm' was raised on POWER 5 and
> 6 due a __vector __int128_t being used as operands without passing the

due to...

> option -msvx to gcc. However, the test doesn't need to use a __int128_t a

 2 spaces ------------^

> unsigned int should work.

The last sentence is confusing and I replace it with:

    This patch replaces "__vector __int128_t" with "__vector unsigned int"
    which requires only -maltivec, available since POWER ISA 2.03, and which
    is already passed to the compiler.

> 2019-01-14  Rogerio A. Cardoso  <rcardoso@linux.ibm.com>
>
> 	* sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: Changed __vector

Missing the entity name -------------------------------------^

> __int128_t to vector unsigned int.

  ^--- Missing tab.

I modified this ChangeLog entry to:

	* sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c:
	(do_test): Changed __vector __int128_t to vector unsigned int.

Modified and pushed as 56054664ccf837fa325692c0359baa62c64491a1.

Thanks!
diff mbox

Patch

From 1a70e67a2fda78bb56c34a882f85653e66bc087d Mon Sep 17 00:00:00 2001
From: Rogerio Alves <rcardoso@linux.ibm.com>
Date: Mon, 14 Jan 2019 07:53:50 -0600
Subject: [PATCH] powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6.

An error: impossible register constraint in 'asm' was raised on POWER 5 and
6 due a __vector __int128_t being used as operands without passing the
option -msvx to gcc. However, the test doesn't need to use a __int128_t a
unsigned int should work.

2019-01-14  Rogerio A. Cardoso  <rcardoso@linux.ibm.com>

	* sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: Changed __vector
__int128_t to vector unsigned int.
---
 sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
index 2dcf5bb..dbe06c8 100644
--- a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
+++ b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
@@ -44,8 +44,8 @@  do_test (void)
   uint32_t* vscr_ptr = vscr;
   uint32_t vscr_word;
   ucontext_t ucp;
-  __vector __int128_t v0 = {0};
-  __vector __int128_t v1 = {0};
+  __vector unsigned int v0 = {0};
+  __vector unsigned int v1 = {0};
 
   /* Set SAT bit in VSCR register.  */
   asm volatile (".machine push;\n"
-- 
2.7.4