From patchwork Fri Apr 24 12:29:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayshao-oc X-Patchwork-Id: 38866 Return-Path: X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from ZXSHCAS2.zhaoxin.com (unknown [203.148.12.82]) by sourceware.org (Postfix) with ESMTPS id 5674738930F7 for ; Fri, 24 Apr 2020 12:29:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5674738930F7 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Mayshao-oc@zhaoxin.com Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 24 Apr 2020 20:29:46 +0800 Received: from localhost.localdomain (124.64.17.172) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 24 Apr 2020 20:29:44 +0800 From: mayshao-oc To: CC: , , , , , , mayshao Subject: [PATCH v3 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors Date: Fri, 24 Apr 2020 20:29:30 +0800 Message-ID: <1587731372-9324-2-git-send-email-mayshao-oc@zhaoxin.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587731372-9324-1-git-send-email-mayshao-oc@zhaoxin.com> References: <1587731372-9324-1-git-send-email-mayshao-oc@zhaoxin.com> MIME-Version: 1.0 X-Originating-IP: [124.64.17.172] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx3.zhaoxin.com (10.29.252.165) X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, RCVD_IN_ABUSEAT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Apr 2020 12:29:53 -0000 From: mayshao To recognize Zhaoxin CPU Vendor ID, add a new architecture type arch_kind_zhaoxin for Vendor Zhaoxin detection. --- sysdeps/x86/cpu-features.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ sysdeps/x86/cpu-features.h | 1 + 2 files changed, 55 insertions(+) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 81a170a..bfb415f 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -466,6 +466,60 @@ init_cpu_features (struct cpu_features *cpu_features) } } } + /* This spells out "CentaurHauls" or " Shanghai ". */ + else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561) + || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61)) + { + unsigned int extended_model, stepping; + + kind = arch_kind_zhaoxin; + + get_common_indices (cpu_features, &family, &model, &extended_model, + &stepping); + + get_extended_indices (cpu_features); + + model += extended_model; + if (family == 0x6) + { + if (model == 0xf || model == 0x19) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= (bit_arch_Slow_SSE4_2); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + else if (family == 0x7) + { + if (model == 0x1b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= bit_arch_Slow_SSE4_2; + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + else if (model == 0x3b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + } else { kind = arch_kind_other; diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index aea83e6..f05d5ce 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -53,6 +53,7 @@ enum cpu_features_kind arch_kind_unknown = 0, arch_kind_intel, arch_kind_amd, + arch_kind_zhaoxin, arch_kind_other };