From patchwork Mon Mar 30 05:33:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "May Shao(BJ-RD)" X-Patchwork-Id: 38655 Return-Path: X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from ZXSHCAS2.zhaoxin.com (unknown [203.148.12.82]) by sourceware.org (Postfix) with ESMTPS id 89A76385B836 for ; Mon, 30 Mar 2020 05:33:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 89A76385B836 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=MayShao@zhaoxin.com Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:53 +0800 Received: from dmdba-HX001EM2.zhaoxin.com (10.29.8.4) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:52 +0800 From: MayShao To: CC: , , , , Subject: [PATCH v2 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors Date: Mon, 30 Mar 2020 13:33:48 +0800 Message-ID: <1585546430-6167-2-git-send-email-MayShao@zhaoxin.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585546430-6167-1-git-send-email-MayShao@zhaoxin.com> References: <1585546430-6167-1-git-send-email-MayShao@zhaoxin.com> MIME-Version: 1.0 X-Originating-IP: [10.29.8.4] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx1.zhaoxin.com (10.29.252.163) X-Spam-Status: No, score=-21.6 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Mar 2020 05:33:59 -0000 To recognize Zhaoxin CPU Vendor ID, add a new architecture type arch_kind_zhaoxin for Vendor Zhaoxin detection. --- sysdeps/x86/cpu-features.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ sysdeps/x86/cpu-features.h | 1 + 2 files changed, 59 insertions(+) -- 2.7.4 保密声明： 本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited. diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 81a170a..4d60553 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -466,6 +466,64 @@ init_cpu_features (struct cpu_features *cpu_features) } } } + /* This spells out "CentaurHauls" or " Shanghai ". */ + else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561) + || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61)) + { + unsigned int extended_model, stepping; + + kind = arch_kind_zhaoxin; + + get_common_indices (cpu_features, &family, &model, &extended_model, + &stepping); + + get_extended_indices (cpu_features); + + + if (family == 0x6) + { + model += extended_model; + if (model == 0xf || model == 0x19) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= (bit_arch_Slow_SSE4_2); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + + if (family == 0x7) + { + model += extended_model; + if (model == 0x1b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= bit_arch_Slow_SSE4_2; + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + + if (model == 0x3b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + } else { kind = arch_kind_other; diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index aea83e6..f05d5ce 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -53,6 +53,7 @@ enum cpu_features_kind arch_kind_unknown = 0, arch_kind_intel, arch_kind_amd, + arch_kind_zhaoxin, arch_kind_other };