From patchwork Mon Dec 9 03:29:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "May Shao(BJ-RD)" X-Patchwork-Id: 36642 Received: (qmail 54805 invoked by alias); 9 Dec 2019 03:29:39 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 54685 invoked by uid 89); 9 Dec 2019 03:29:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.6 required=5.0 tests=AWL, BAYES_00, BODY_8BITS, GARBLED_BODY, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=H*r:0800, shanghai, Shanghai X-HELO: ZXSHCAS2.zhaoxin.com From: MayShao To: CC: , , , , Subject: [PATCH 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors Date: Mon, 9 Dec 2019 11:29:33 +0800 Message-ID: <1575862175-5044-2-git-send-email-MayShao@zhaoxin.com> In-Reply-To: <1575862175-5044-1-git-send-email-MayShao@zhaoxin.com> References: <1575862175-5044-1-git-send-email-MayShao@zhaoxin.com> MIME-Version: 1.0 Return-Path: MayShao@zhaoxin.com To recognize Zhaoxin CPU Vendor ID, add a new architecture type arch_kind_zhaoxin for Vendor Zhaoxin detection. Checked on x86_64-linux-gnu. Signed-off-by: MayShao --- sysdeps/x86/cpu-features.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ sysdeps/x86/cpu-features.h | 1 + 2 files changed, 60 insertions(+) -- 2.7.4 保密声明： 本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited. diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 4bab154..9174c9d 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -466,6 +466,65 @@ init_cpu_features (struct cpu_features *cpu_features) } } } + /* This spells out "CentaurHauls" or " Shanghai ". */ + else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561) + || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61)) + { + unsigned int extended_model; + + kind = arch_kind_zhaoxin; + + get_common_indices (cpu_features, &family, &model, &extended_model, + &stepping); + + get_extended_indices (cpu_features); + + + if (family == 0x6) + { + model += extended_model; + if (model == 0xf || model == 0x19) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= (bit_arch_Slow_SSE4_2 + | bit_arch_Prefer_MAP_32BIT_EXEC); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + + if (family == 0x7) + { + model += extended_model; + if (model == 0x1b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_Slow_SSE4_2] + |= bit_arch_Slow_SSE4_2; + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + + if (model == 0x3b) + { + cpu_features->feature[index_arch_AVX_Usable] + &= (~bit_arch_AVX_Usable + & ~bit_arch_AVX2_Usable); + + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } + } + } else { kind = arch_kind_other; diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 03a9b2a..cab55ef 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -53,6 +53,7 @@ enum cpu_features_kind arch_kind_unknown = 0, arch_kind_intel, arch_kind_amd, + arch_kind_zhaoxin, arch_kind_other };