From patchwork Tue Aug 20 21:19:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 34199 Received: (qmail 111508 invoked by alias); 20 Aug 2019 21:19:56 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 111449 invoked by uid 89); 20 Aug 2019 21:19:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH 3/4] [powerpc] fesetenv: optimize FPSCR access Date: Tue, 20 Aug 2019 16:19:44 -0500 Message-Id: <1566335985-14601-4-git-send-email-pc@us.ibm.com> In-Reply-To: <1566335985-14601-1-git-send-email-pc@us.ibm.com> References: <1566335985-14601-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fesetenv() reads the current value of the Floating-Point Status and Control Register (FPSCR) to determine the difference between the current state of exception enables and the newly requested state. All of these bits are also returned by the lighter weight 'mffsl' instruction used by fegetenv_status(). Use that instead. Also, remove a local macro _FPU_MASK_ALL in favor of a common macro, FPU_ENABLES_MASK from fenv_libc.h. Finally, use a local variable ('new') in favor of a pointer dereference ('*envp'). 2019-08-20 Paul A. Clarke * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Utilize lightweight FPSCR read. (_FPU_MASK_ALL): Delete. --- sysdeps/powerpc/fpu/fesetenv.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 009a4f0..5ca15c7 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -19,8 +19,6 @@ #include #include -#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM) - int __fesetenv (const fenv_t *envp) { @@ -28,25 +26,23 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; - old.fenv = fegetenv_register (); - if (old.l == new.l) - return 0; + old.fenv = fegetenv_status (); /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ - if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) + if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0) (void) __fe_nomask_env_priv (); /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) + if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0) (void)__fe_mask_env (); - fesetenv_register (*envp); + fesetenv_register (new.fenv); /* Success. */ return 0;