From patchwork Wed Apr 11 21:16:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 26688 Received: (qmail 117673 invoked by alias); 11 Apr 2018 21:16:31 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117583 invoked by uid 89); 11 Apr 2018 21:16:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=mvn X-HELO: mail-qt0-f179.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=k2PURCzAKrYq84Ui92ryKubW2SLZnlspVYb5f72V3gg=; b=aToadpgHGBBaz4MgqVDGzLHJxibqFjprq1bhooDs0gIyHNSE1h348rZUizeYfQhXDf mbh7DBv/Gagx1bc57uvyjzlRrujbZFn+cqO6YmsTYQYnUfW4NMXzrniSU++NI+sGP/RG SuePiccFNIGUnbyjTVy9z0D237x6cM9v9OoCP1JQ7vtu4hJX0DLdTfWrXkKjgtnm5AmU kj9zdtflms95eYkwD9mHiDrBvFk8gKs/R2VPR9OOAm7Dcnlo2zqXg0ZbyOjSOpnBxvN8 ZdlPRH7oqFyuohEKt2wja01iZ1D3hHIHaHVpWsnZfJpqE6EdL9Soh/kxe2YCfDBDCQHw h//w== X-Gm-Message-State: ALQs6tBy9oM2oDcQVXEf8aa1EZsDZhbMWiFl2S20EMfBxBIzGztPqs+b cPxMZAI00WY/vz/mXlXLw1jH1pPibAA= X-Google-Smtp-Source: AIpwx48PlxKkbJCJRFt71UL0cN6Xw8kDJvbC+GDw9aArTU+rvKi0aAxX7k6eN5EWzwBAygqzsFFfvQ== X-Received: by 10.200.81.200 with SMTP id d8mr9608352qtn.1.1523481387207; Wed, 11 Apr 2018 14:16:27 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 2/4] arm: Fix armv7 neon strcmp on ARM mode Date: Wed, 11 Apr 2018 18:16:16 -0300 Message-Id: <1523481378-16290-2-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv7 neon strcmp uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Also, even if the implementation is fixed to not use thumb instructions it was clearly not proper checked in ARM mode: the 'prepare_mask' does not build (it sets the 'mvn' instruction to use register predicate in shift amount). This patch fixes it by using a S2HI plus mvn to mimic the expected nor operation. Checked on arm-linux-gnueabihf (with -marm and -mthumb mode). [BZ #23031] * sysdeps/arm/armv7/strcmp.S [!__thumb__] (prepare_mask): Fix build and logic. --- ChangeLog | 4 ++++ sysdeps/arm/armv7/strcmp.S | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/sysdeps/arm/armv7/strcmp.S b/sysdeps/arm/armv7/strcmp.S index 060b865..a20b3e5 100644 --- a/sysdeps/arm/armv7/strcmp.S +++ b/sysdeps/arm/armv7/strcmp.S @@ -82,8 +82,7 @@ #define data2 r3 #define syndrome tmp2 - -#ifndef NO_THUMB +#ifdef __thumb__ /* This code is best on Thumb. */ .thumb @@ -97,7 +96,8 @@ #else /* In ARM code we don't have ORN, but we can use MVN with a register shift. */ .macro prepare_mask mask_reg, nbits_reg - mvn \mask_reg, const_m1, S2HI \nbits_reg + S2HI \mask_reg, const_m1, \nbits_reg + mvn \mask_reg, \mask_reg .endm .macro apply_mask data_reg, mask_reg orr \data_reg, \data_reg, \mask_reg