From patchwork Fri Oct 17 15:31:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 3272 Received: (qmail 17007 invoked by alias); 17 Oct 2014 15:31:40 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 16873 invoked by uid 89); 17 Oct 2014 15:31:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f41.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=fhfDSazZ2EYwLQXVmWehp2UxIfJM39W7wfBoGr1F7OY=; b=j3yEsmCaNEdG53/aZLvvOH/yH3OOBQtAq83SGFpyM3+ng6oO9mAug3PCSfAZLXQEfV eztoKUdiaVtublzzBEtSxocR80OCb9T8ZCokh7gC4J/C8AmcT0Gp5YrFZzemA+rsMFjk htm7hGYQl8yYHfJNRe0OIYCEzydxvFdhVCsqk+QpFi3nBcAi7MM5yJy7L6OCBYGOjE6c 9AdbUg/mQvgTLGpax/j4YsXpRwBzt3PVakroBlALyBbaSC7+w5/lYrH7obgW7A0Nqc8N E9rKXe5X/Fr45LLwpZFYrxJoPOgG9ji4hLbah4tiDmPPmRwOHmu9iJ5dt+q2BucE/fIM vb2w== X-Gm-Message-State: ALoCoQnReJAqMPcjLGUzLFurGuVb0j9WBkdRVpqfgURy7AAaNSRjpa8CFigzCGtuaqVvHQuSv79W X-Received: by 10.194.184.12 with SMTP id eq12mr11798542wjc.100.1413559894897; Fri, 17 Oct 2014 08:31:34 -0700 (PDT) From: Will Newton To: libc-alpha@sourceware.org Subject: [PATCH 5/5] sysdeps/arm/bits/atomic.h: Switch to generic implementation Date: Fri, 17 Oct 2014 16:31:22 +0100 Message-Id: <1413559882-959-6-git-send-email-will.newton@linaro.org> In-Reply-To: <1413559882-959-1-git-send-email-will.newton@linaro.org> References: <1413559882-959-1-git-send-email-will.newton@linaro.org> Switch the ARM port to using the generic GCC intrinsic based atomic implementation when the version of gcc used supports it. ChangeLog: 2014-10-15 Will Newton * sysdeps/arm/bits/atomic.h: Include sysdeps/generic/atomic_types.h. Remove existing atomic tyepdefs. [__GNUC_PREREQ (4, 7) && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4]: (__ARCH_ATOMIC_64_SUPPORTED): Define to 0. Include sysdeps/generic/atomic.h. Remove existing atomic defines. --- sysdeps/arm/bits/atomic.h | 99 ++++------------------------------------------- 1 file changed, 8 insertions(+), 91 deletions(-) diff --git a/sysdeps/arm/bits/atomic.h b/sysdeps/arm/bits/atomic.h index 88cbe67..eefb5e5 100644 --- a/sysdeps/arm/bits/atomic.h +++ b/sysdeps/arm/bits/atomic.h @@ -16,22 +16,7 @@ License along with the GNU C Library. If not, see . */ -#include - -typedef int8_t atomic8_t; -typedef uint8_t uatomic8_t; -typedef int_fast8_t atomic_fast8_t; -typedef uint_fast8_t uatomic_fast8_t; - -typedef int32_t atomic32_t; -typedef uint32_t uatomic32_t; -typedef int_fast32_t atomic_fast32_t; -typedef uint_fast32_t uatomic_fast32_t; - -typedef intptr_t atomicptr_t; -typedef uintptr_t uatomicptr_t; -typedef intmax_t atomic_max_t; -typedef uintmax_t uatomic_max_t; +#include void __arm_link_error (void); @@ -52,84 +37,13 @@ void __arm_link_error (void); a pattern to do this efficiently. */ #if __GNUC_PREREQ (4, 7) && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 -# define atomic_exchange_acq(mem, value) \ - __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE) - -# define atomic_exchange_rel(mem, value) \ - __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE) - -/* Atomic exchange (without compare). */ - -# define __arch_exchange_8_int(mem, newval, model) \ - (__arm_link_error (), (typeof (*mem)) 0) - -# define __arch_exchange_16_int(mem, newval, model) \ - (__arm_link_error (), (typeof (*mem)) 0) - -# define __arch_exchange_32_int(mem, newval, model) \ - __atomic_exchange_n (mem, newval, model) - -# define __arch_exchange_64_int(mem, newval, model) \ - (__arm_link_error (), (typeof (*mem)) 0) - -/* Compare and exchange with "acquire" semantics, ie barrier after. */ - -# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ - __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ - mem, new, old, __ATOMIC_ACQUIRE) - -# define atomic_compare_and_exchange_val_acq(mem, new, old) \ - __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ - mem, new, old, __ATOMIC_ACQUIRE) - -/* Compare and exchange with "release" semantics, ie barrier before. */ - -# define atomic_compare_and_exchange_bool_rel(mem, new, old) \ - __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ - mem, new, old, __ATOMIC_RELEASE) - -# define atomic_compare_and_exchange_val_rel(mem, new, old) \ - __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ - mem, new, old, __ATOMIC_RELEASE) - -/* Compare and exchange. - For all "bool" routines, we return FALSE if exchange succesful. */ - -# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \ - ({__arm_link_error (); 0; }) - -# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \ - ({__arm_link_error (); 0; }) - -# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \ - ({ \ - typeof (*mem) __oldval = (oldval); \ - !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ - model, __ATOMIC_RELAXED); \ - }) - -# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ - ({__arm_link_error (); 0; }) - -# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \ - ({__arm_link_error (); oldval; }) - -# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \ - ({__arm_link_error (); oldval; }) - -# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \ - ({ \ - typeof (*mem) __oldval = (oldval); \ - __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ - model, __ATOMIC_RELAXED); \ - __oldval; \ - }) - -# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ - ({__arm_link_error (); oldval; }) +# define __ARCH_ATOMIC_64_SUPPORTED 0 +# include #elif defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 + /* Atomic compare and exchange. */ + # define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ __sync_val_compare_and_swap ((mem), (oldval), (newval)) #else @@ -138,8 +52,10 @@ void __arm_link_error (void); #endif #if !__GNUC_PREREQ (4, 7) || !defined (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) + /* We don't support atomic operations on any non-word types. So make them link errors. */ + # define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \ ({ __arm_link_error (); oldval; }) @@ -148,6 +64,7 @@ void __arm_link_error (void); # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ ({ __arm_link_error (); oldval; }) + #endif /* An OS-specific bits/atomic.h file will define this macro if