[v5,16/17] Documentation for the RISC-V 32-bit port
Commit Message
There is already RISC-V 64-bit port information in the documentation.
Let's add some documentation entries for the RISC-V 32-bit as well.
---
NEWS | 11 ++++++++++-
README | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
Comments
On Wed, 19 Aug 2020, Alistair Francis via Libc-alpha wrote:
> There is already RISC-V 64-bit port information in the documentation.
> Let's add some documentation entries for the RISC-V 32-bit as well.
LGTM.
Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
Maciej
@@ -9,7 +9,16 @@ Version 2.33
Major new features:
- [Add new features here]
+
+* Support for the RISC-V ISA running on Linux has been expanded to run on
+ 32-bit hardware. This is supported for the following ISA and ABI pairs:
+
+ - rv32imac ilp32
+ - rv32imafdc ilp32
+ - rv32imafdc ilp32d
+
+ The 32-bit RISC-V port requires at least Linux 5.4, GCC 7.1 and binutils
+ 2.28.
Deprecated and removed features, and other changes affecting compatibility:
@@ -39,6 +39,7 @@ The GNU C Library supports these configurations for using Linux kernels:
powerpc64*-*-linux-gnu Big-endian and little-endian.
s390-*-linux-gnu
s390x-*-linux-gnu
+ riscv32-*-linux-gnu
riscv64-*-linux-gnu
sh[34]-*-linux-gnu
sparc*-*-linux-gnu