From patchwork Mon Oct 15 11:52:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 29741 Received: (qmail 12204 invoked by alias); 15 Oct 2018 11:54:33 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 11321 invoked by uid 89); 15 Oct 2018 11:54:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*RU:209.85.210.193, Hx-spam-relays-external:209.85.210.193, fma X-HELO: mail-pf1-f193.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b3PUUtKmdYosbs11MsDchrY8bAxWnPQCeez1wX31Rtk=; b=Ftry9tpsylulNNb+O6ouXfcjFAYvm6pA+lscobqOxn4oIlmsNy97Eea0btETdP2AVU X9KzPDPPVSTCDmsevZfwyUPotstGPFuNJZ94UEXeWvLQBNeME5YTncb6Lpm5xT/5LPX9 6SZK1VlpeNYbg0feOhgRKkaWiDGcHYkVILn9a93g/eIm6HtpiFR7WJdIHZWhZFD8akIs KKZw7BjGGyjXTXLMfTpukOuRijuKspN9ViR0h3fhZSt6Ax1llKllsZnNfTRQS1OWq0/R 3QNQYcqk47aSlmv9UAUreceJOQKOvEK42fQ11gAxnPXiL1AqNj/q8Ve+8UUFtzJ0z6Nl 0sYw== Return-Path: From: Zong Li To: joseph@codesourcery.com, palmer@dabbelt.com, darius@bluespec.com, andrew@sifive.com, dj@redhat.com, libc-alpha@sourceware.org Cc: jimw@sifive.com, kito@andestech.com, greentime@andestech.com, zongbox@gmail.com Subject: [PATCH 2/2] soft-fp: Add the lack of implementation for 128 bit self-contained Date: Mon, 15 Oct 2018 19:52:31 +0800 Message-Id: <04da5a0bfe2816e47c7b52c7e82dc6ec87db7527.1539595555.git.zongbox@gmail.com> In-Reply-To: References: Here only add the lack of implementation when building the RISC-V 32-bit port. These marcos are used when the following situations occur at the same time: soft-fp fma, ldbl-128 and 32-bit _FP_W_TYPE_SIZE. The RISC-V 32-bit port is the first port which use all three together. This is the building flow about the situation: When building soft-fp/s_fmal.c, there uses the FP_FMA_Q in __fmal. The _FP_W_TYPE_SIZE is defined to 32-bit in sysdeps/riscv/sfp-machine.h, so the FP_FMA_Q was defined to _FP_FMA (Q, 4, 8, R, X, Y, Z) in soft-fp/quad.h. Something in the soft-fp/quad.h: #if _FP_W_TYPE_SIZE < 64 # define FP_FMA_Q(R, X, Y, Z) _FP_FMA (Q, 4, 8, R, X, Y, Z) #else # define FP_FMA_Q(R, X, Y, Z) _FP_FMA (Q, 2, 4, R, X, Y, Z) #endif Finally, in _FP_FMA (fs, wc, dwc, R, X, Y, Z), it will use the _FP_FRAC_HIGHBIT_DW_##dwc macro, and it will be expanded to _FP_FRAC_HIGHBIT_DW_8, but the _FP_FRAC_HIGHBIT_DW_8 is not be implemented in soft-fp/op-8.h. there is only _FP_FRAC_HIGHBIT_DW_1, _FP_FRAC_HIGHBIT_DW_2 and _FP_FRAC_HIGHBIT_DW_4 in the soft-fp/op-*.h. After this modification, we can pass the soft floating testing of glibc testsuites on RV32. * soft-fp/op-8.h: Add macros for RV32 use. --- ChangeLog | 1 + soft-fp/op-8.h | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/ChangeLog b/ChangeLog index bb30093..47d3cf2 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,6 +1,7 @@ 2018-10-15 Zong Li * soft-fp/op-4.h: Fix wrong calculation of division. + * soft-fp/op-8.h: Add macros for RV32 use. 2018-10-14 Paul Eggert diff --git a/soft-fp/op-8.h b/soft-fp/op-8.h index ffed258..45b019e 100644 --- a/soft-fp/op-8.h +++ b/soft-fp/op-8.h @@ -35,6 +35,7 @@ /* We need just a few things from here for op-4, if we ever need some other macros, they can be added. */ #define _FP_FRAC_DECL_8(X) _FP_W_TYPE X##_f[8] +#define _FP_FRAC_SET_8(X, I) __FP_FRAC_SET_8 (X, I) #define _FP_FRAC_HIGH_8(X) (X##_f[7]) #define _FP_FRAC_LOW_8(X) (X##_f[0]) #define _FP_FRAC_WORD_8(X, w) (X##_f[w]) @@ -147,4 +148,110 @@ } \ while (0) +#define _FP_FRAC_ADD_8(R, X, Y) \ + do \ + { \ + _FP_W_TYPE fa8_c = 0; \ + for (int fa8_i = 0; fa8_i < 8; ++fa8_i) \ + { \ + R##_f[fa8_i] = X##_f[fa8_i] + Y##_f[fa8_i] + fa8_c; \ + fa8_c = (fa8_c \ + ? R##_f[fa8_i] <= X##_f[fa8_i] \ + : R##_f[fa8_i] < X##_f[fa8_i]); \ + } \ + } \ + while (0) + +#define _FP_FRAC_SUB_8(R, X, Y) \ + do \ + { \ + _FP_W_TYPE fs8_c = 0; \ + for (int fs8_i = 0; fs8_i < 8; ++fs8_i) \ + { \ + R##_f[fs8_i] = X##_f[fs8_i] - Y##_f[fs8_i] - fs8_c; \ + fs8_c = (fs8_c \ + ? R##_f[fs8_i] >= X##_f[fs8_i] \ + : R##_f[fs8_i] > X##_f[fs8_i]); \ + } \ + } \ + while (0) + +#define _FP_FRAC_CLZ_8(R, X) \ + do \ + { \ + if (X##_f[7]) \ + __FP_CLZ ((R), X##_f[7]); \ + else if (X##_f[6]) \ + { \ + __FP_CLZ ((R), X##_f[6]); \ + (R) += _FP_W_TYPE_SIZE; \ + } \ + else if (X##_f[5]) \ + { \ + __FP_CLZ ((R), X##_f[5]); \ + (R) += _FP_W_TYPE_SIZE * 2; \ + } \ + else if (X##_f[4]) \ + { \ + __FP_CLZ ((R), X##_f[4]); \ + (R) += _FP_W_TYPE_SIZE * 3; \ + } \ + else if (X##_f[3]) \ + { \ + __FP_CLZ ((R), X##_f[3]); \ + (R) += _FP_W_TYPE_SIZE * 4; \ + } \ + else if (X##_f[2]) \ + { \ + __FP_CLZ ((R), X##_f[2]); \ + (R) += _FP_W_TYPE_SIZE * 5; \ + } \ + else if (X##_f[1]) \ + { \ + __FP_CLZ ((R), X##_f[1]); \ + (R) += _FP_W_TYPE_SIZE * 6; \ + } \ + else \ + { \ + __FP_CLZ ((R), X##_f[0]); \ + (R) += _FP_W_TYPE_SIZE * 7; \ + } \ + } \ + while (0) + +#define _FP_MINFRAC_8 0, 0, 0, 0, 0, 0, 0, 1 + +#define _FP_FRAC_NEGP_8(X) ((_FP_WS_TYPE) X##_f[7] < 0) +#define _FP_FRAC_ZEROP_8(X) \ + ((X##_f[0] | X##_f[1] | X##_f[2] | X##_f[3] \ + | X##_f[4] | X##_f[5] | X##_f[6] | X##_f[7]) == 0) +#define _FP_FRAC_HIGHBIT_DW_8(fs, X) \ + (_FP_FRAC_HIGH_DW_##fs (X) & _FP_HIGHBIT_DW_##fs) + + +#define _FP_FRAC_COPY_4_8(D, S) \ + do \ + { \ + D##_f[0] = S##_f[0]; \ + D##_f[1] = S##_f[1]; \ + D##_f[2] = S##_f[2]; \ + D##_f[3] = S##_f[3]; \ + } \ + while (0) + +#define _FP_FRAC_COPY_8_4(D, S) \ + do \ + { \ + D##_f[0] = S##_f[0]; \ + D##_f[1] = S##_f[1]; \ + D##_f[2] = S##_f[2]; \ + D##_f[3] = S##_f[3]; \ + D##_f[4] = D##_f[5] = D##_f[6] = D##_f[7]= 0; \ + } \ + while (0) + +#define __FP_FRAC_SET_8(X, I7, I6, I5, I4, I3, I2, I1, I0) \ + (X##_f[7] = I7, X##_f[6] = I6, X##_f[5] = I5, X##_f[4] = I4, \ + X##_f[3] = I3, X##_f[2] = I2, X##_f[1] = I1, X##_f[0] = I0) + #endif /* !SOFT_FP_OP_8_H */