From patchwork Wed Jun 3 16:25:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 39436 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0ED53388C007; Wed, 3 Jun 2020 16:34:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0ED53388C007 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1591202057; bh=axoy55d/ZNrM3hDShVE/qIVstSpplbdQ9QJnL1TUABE=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=hwnqsWLuJ/uKBC5zQYmeVEbmhsrmng+fMtF8yleiBbTjlLuRXxbnDKR5/hNw1TIkB 0byz5XwONPsTW7RBZsnvV0zOUQgKBAUxS6zNSz2uanfeZSijKkBgVEmg+SwYCCNJTs 8DmcUmn4OuH5t0+RiytFZNzgq0+jqQvncm1Jqh9c= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from esa3.hgst.iphmx.com (esa3.hgst.iphmx.com [216.71.153.141]) by sourceware.org (Postfix) with ESMTPS id 2758B388A82C for ; Wed, 3 Jun 2020 16:34:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 2758B388A82C IronPort-SDR: 0Di5Ca8F9+fkANVTv4EAIP9SA7AvHvXFzFNngOEWEwN5WpMfCweASMqUhZqA/ENtqKWi3QDu36 OCm5kwgbewEiiHKHMxkkkfwIZoUQLOVSYFIni7d3H6NOJVrPNoZK6sImL+8ZPH1VsHfJVlCdb+ BGhOtCWVoTapWRUUVP6JUDs8MiugLv/DmYpklBORO8FQ5AfKLUk3z+jcMlH7fd3DCed9wQ2Zib L/jGlkfFXs/OLT1ibez3G0srQqbv4VONG6NjLKfPrvQAvDs5cOBNzgiZpil9+d07c40F43HiSF Jdg= X-IronPort-AV: E=Sophos;i="5.73,468,1583164800"; d="scan'208";a="143452216" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Jun 2020 00:34:10 +0800 IronPort-SDR: 68xtpGWWGMGPQyyYk3xpLPz+b6WfuBk/iV98YelCAnUifBRniskygS+EffW2k1wB+vFrNHyV60 MsZjn7wTC6Jcb3Pw1VtrNEYGBdPoqOC7Q= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2020 09:23:47 -0700 IronPort-SDR: 5T3/V2VwQ9gz6AVl4kvRF1b7DHXoYRJz8Pdf/ulXUCUJfzHH6HNDgywL+xNefbejjcFGeG2iKd t5upDIXTtxjQ== WDCIronportException: Internal Received: from cne220230.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.57.144]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Jun 2020 09:34:09 -0700 To: libc-alpha@sourceware.org Subject: [PATCH v2 00/18] glibc port for 32-bit RISC-V (RV32) Date: Wed, 3 Jun 2020 09:25:24 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alistair Francis via Libc-alpha From: Alistair Francis Reply-To: Alistair Francis Cc: alistair.francis@wdc.com Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" This patch set contains the glibc port for 32-bit RISC-V. This is based on the original work from Zong Li [1] and has been updated to use a 64-bit time_t. This requires a 5.4+ kernel and all of the testing has been done using the 5.4 stable kernel. Nothing fails when running ./scripts/build-many-glibcs.py (for all targets) on my x86-64 machine. This is the current list of tests that fail when running inside QEMU RV32 system emulation on the 5.4 kernel: FAIL: elf/tst-ldconfig-ld_so_conf-update FAIL: io/tst-lockf FAIL: misc/test-errno-linux FAIL: nss/tst-nss-files-hosts-long FAIL: resolv/tst-resolv-res_init-thread FAIL: stdio-common/bug22 FAIL: stdlib/tst-strfrom FAIL: stdlib/tst-strfrom-locale ---Links--- 1: https://sourceware.org/ml/libc-alpha/2018-07/msg00892.html The latest version of my work can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.next This specific version can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.2 Alistair Francis (9): RISC-V: Use 64-bit time_t and off_t for RV32 and RV64 RISC-V: Define __NR_* as __NR_*_time64/64 for 32-bit RISC-V: Add support for 32-bit vDSO calls RISC-V: Add arch-syscall.h for RV32 RISC-V: nptl: update default pthread-offsets.h riscv32: Add an architecture ipctypes.h RISC-V: Add ABI lists RISC-V: Add the RV32 libm-test-ulps riscv32: Specify the arch_minimum_kernel as 5.4 Zong Li (9): RISC-V: Support dynamic loader for the 32-bit RISC-V: Add path of library directories for the 32-bit RISC-V: The ABI implementation for 32-bit RISC-V: Hard float support for 32-bit RISC-V: Fix llrint and llround missing exceptions on RV32 RISC-V: Build Infastructure for 32-bit RISC-V: Add rv32 path to RTLDLIST in ldd Documentation for the RISC-V 32-bit port Add RISC-V 32-bit target to build-many-glibcs.py NEWS | 6 + README | 1 + scripts/build-many-glibcs.py | 15 + sysdeps/riscv/bits/wordsize.h | 4 +- sysdeps/riscv/nptl/bits/pthreadtypes-arch.h | 10 +- sysdeps/riscv/nptl/bits/struct_rwlock.h | 27 +- sysdeps/riscv/nptl/pthread-offsets.h | 13 +- sysdeps/riscv/preconfigure | 6 +- sysdeps/riscv/rv32/Implies-after | 1 + .../riscv/rv32/fix-fp-int-convert-overflow.h | 38 + sysdeps/riscv/rv32/rvd/Implies | 3 + sysdeps/riscv/rv32/rvd/libm-test-ulps | 1401 +++++++++++ sysdeps/riscv/rv32/rvd/libm-test-ulps-name | 1 + sysdeps/riscv/rv32/rvd/s_lrint.c | 31 + sysdeps/riscv/rv32/rvd/s_lround.c | 31 + sysdeps/riscv/rv32/rvf/Implies | 1 + sysdeps/riscv/rv32/rvf/s_lrintf.c | 31 + sysdeps/riscv/rv32/rvf/s_lroundf.c | 31 + sysdeps/riscv/sfp-machine.h | 27 +- sysdeps/riscv/sys/asm.h | 5 +- sysdeps/unix/sysv/linux/riscv/Makefile | 4 +- .../unix/sysv/linux/riscv/bits/environments.h | 85 + sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h | 35 + sysdeps/unix/sysv/linux/riscv/bits/time64.h | 36 + sysdeps/unix/sysv/linux/riscv/bits/timesize.h | 22 + sysdeps/unix/sysv/linux/riscv/c++-types.data | 67 + sysdeps/unix/sysv/linux/riscv/configure | 43 + sysdeps/unix/sysv/linux/riscv/configure.ac | 12 + sysdeps/unix/sysv/linux/riscv/dl-cache.h | 17 +- .../unix/sysv/linux/riscv/jmp_buf-macros.h | 53 + sysdeps/unix/sysv/linux/riscv/kernel_stat.h | 23 + sysdeps/unix/sysv/linux/riscv/ld.abilist | 5 + sysdeps/unix/sysv/linux/riscv/ldconfig.h | 2 +- sysdeps/unix/sysv/linux/riscv/ldd-rewrite.sed | 2 +- .../sysv/linux/riscv/libBrokenLocale.abilist | 1 + sysdeps/unix/sysv/linux/riscv/libanl.abilist | 4 + sysdeps/unix/sysv/linux/riscv/libc.abilist | 2099 +++++++++++++++++ .../unix/sysv/linux/riscv/libcrypt.abilist | 2 + sysdeps/unix/sysv/linux/riscv/libdl.abilist | 9 + sysdeps/unix/sysv/linux/riscv/libm.abilist | 940 ++++++++ .../unix/sysv/linux/riscv/libpthread.abilist | 213 ++ .../unix/sysv/linux/riscv/libresolv.abilist | 79 + sysdeps/unix/sysv/linux/riscv/librt.abilist | 35 + .../sysv/linux/riscv/libthread_db.abilist | 40 + sysdeps/unix/sysv/linux/riscv/libutil.abilist | 6 + sysdeps/unix/sysv/linux/riscv/rv32/Implies | 3 + .../unix/sysv/linux/riscv/rv32/arch-syscall.h | 283 +++ sysdeps/unix/sysv/linux/riscv/shlib-versions | 10 +- sysdeps/unix/sysv/linux/riscv/sysdep.h | 80 +- 49 files changed, 5868 insertions(+), 25 deletions(-) create mode 100644 sysdeps/riscv/rv32/Implies-after create mode 100644 sysdeps/riscv/rv32/fix-fp-int-convert-overflow.h create mode 100644 sysdeps/riscv/rv32/rvd/Implies create mode 100644 sysdeps/riscv/rv32/rvd/libm-test-ulps create mode 100644 sysdeps/riscv/rv32/rvd/libm-test-ulps-name create mode 100644 sysdeps/riscv/rv32/rvd/s_lrint.c create mode 100644 sysdeps/riscv/rv32/rvd/s_lround.c create mode 100644 sysdeps/riscv/rv32/rvf/Implies create mode 100644 sysdeps/riscv/rv32/rvf/s_lrintf.c create mode 100644 sysdeps/riscv/rv32/rvf/s_lroundf.c create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/environments.h create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/time64.h create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/timesize.h create mode 100644 sysdeps/unix/sysv/linux/riscv/c++-types.data create mode 100644 sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h create mode 100644 sysdeps/unix/sysv/linux/riscv/kernel_stat.h create mode 100644 sysdeps/unix/sysv/linux/riscv/ld.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libBrokenLocale.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libanl.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libc.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libcrypt.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libdl.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libm.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libpthread.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libresolv.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/librt.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libthread_db.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/libutil.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/Implies create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/arch-syscall.h