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[36.226.198.98]) by smtp.gmail.com with ESMTPSA id y69sm15646861pfg.171.2022.01.17.20.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 20:32:11 -0800 (PST) From: Vincent Chen To: libc-alpha@sourceware.org, palmer@dabbelt.com, darius@bluespec.com, andrew@sifive.com, dj@redhat.com Subject: [PATCH v2 0/2] RISC-V: Add vector ISA support Date: Tue, 18 Jan 2022 12:31:57 +0800 Message-Id: <20220118043159.27521-1-vincent.chen@sifive.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: greentime.hu@sifive.com, kito.cheng@sifive.com, Vincent Chen Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" According to the feedback for the version 1 patch set, only the "RISC-V: Remove riscv-specific sigcontext.h" patch remains in this version patch set. It means that MINSIGSTKSZ, SIGSTKSZ, and PTHREAD_STACK_MIN are not changed after introducing the V-extension support. Therefore, the current definition of the above stack size is insufficient to backup all vector registers. In this circumstance, users have to use the mechanisms submitted by H.J. Lu https://sourceware.org/git/?p=glibc.git;a=commit;h=6c57d320484988e87e446e2e60ce42816bf51d53 and https://sourceware.org/git/?p=glibc.git;a=commit;h=5d98a7dae955bafa6740c26eaba9c86060ae0344 to obtain the appropriate size of the current system setting. Besides, a new calling convention using vector registers to transfer argument or return value probably be proposed in the feature. It may cause the resolved functions and audit functions to corrupt the content of the vector registers, which are used as argument registers and address return registers. To avoid this problem, this patch set includes Hsiangkai Wang's patch to enable the Glibc dynamic loader to directly resolve the function symbols whose calling convention is incompatible with the standard calling convention. The corresponding implementation in Binutils can be found in https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8155b8539b55bca87378129e02009cd8907d8c8c. Hsiangkai Wang (1): riscv: Resolve symbols directly for symbols with STO_RISCV_VARIANT_CC. Vincent Chen (1): RISC-V: remove riscv-specific sigcontext.h elf/elf.h | 7 +++++ manual/platform.texi | 6 +++++ .../sigcontext.h => riscv/dl-dtprocnum.h} | 22 +++++----------- sysdeps/riscv/dl-machine.h | 26 +++++++++++++++++++ 4 files changed, 45 insertions(+), 16 deletions(-) rename sysdeps/{unix/sysv/linux/riscv/bits/sigcontext.h => riscv/dl-dtprocnum.h} (55%)