From patchwork Sat Sep 12 13:44:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 40399 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30E163877021; Sat, 12 Sep 2020 13:44:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 30E163877021 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1599918287; bh=hZfAMcN0AUWM1+eT3cjyftSmN5FkteX0Ktv1BBiajAU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=ynrNLTZyaPnaNvhBKXUmzydXtoQGBhTaIr+5Roo1Ktw4zFBUAocEdBFSFR/qD/kmS TBUNqIbM7t5C7XndnEdoGQx2ghACOYJTUiPAZGIi7f0SMjCpyIepP8sUIAOLdkGqfK ytxlXdeo8GVKc7M62chlitZHb82LJHXm8vE6CqQQ= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by sourceware.org (Postfix) with ESMTPS id 5C566386EC47 for ; Sat, 12 Sep 2020 13:44:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5C566386EC47 Received: by mail-pg1-x544.google.com with SMTP id d13so105102pgl.6 for ; Sat, 12 Sep 2020 06:44:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hZfAMcN0AUWM1+eT3cjyftSmN5FkteX0Ktv1BBiajAU=; b=GPGTzWz2LUUDhmKWl4kBNFqJOF8cpG2EMqIB2zU1d+X9wmHW14SxloTnSFABw/LxQJ csWgKv9ZAdmMSc8L7vVrwwbpaTxf6aT6UQI4Vq5oK6347oI34Rol16k/BOIN/wNqSQaj bhDP+RK8425IaVpln/zcZ/coEkyUBetuadOLt06T5/7nA7pjSYG/ZrtIohRPq350z3+r KoKEWxzzZ4goDPndDjxS82wlcOJz5xW5pfhdEgD8jud9oJaTwTKwg8eLjUhfmB1GsBEH HpOP0EvjtGKC2+MP6A6/07XcdG/6F1IbL50Dp+1072I9w+QqxcMCoFuGvsRMq8y86tjc n9Gg== X-Gm-Message-State: AOAM532laWrxTKPQecea4LdJvwAp53LB1XqE0QJC3s5k71CcV7mA66jw 8zRnV6hKJoLZ80kMii34Aes= X-Google-Smtp-Source: ABdhPJyReEf992PTnbXod/t6pBulHshavL86e8aoaxIbi5Om9krEfU2CbG3toWA7SqrJxa/gX9jRNQ== X-Received: by 2002:a63:2e86:: with SMTP id u128mr4911520pgu.135.1599918283376; Sat, 12 Sep 2020 06:44:43 -0700 (PDT) Received: from gnu-cfl-2.localdomain (c-69-181-90-243.hsd1.ca.comcast.net. [69.181.90.243]) by smtp.gmail.com with ESMTPSA id r3sm5271605pfh.88.2020.09.12.06.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Sep 2020 06:44:42 -0700 (PDT) Received: from gnu-cfl-2.localdomain (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 125A71A021E; Sat, 12 Sep 2020 06:44:42 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH 0/3] ld.so: Add --list-tunables to print tunable values Date: Sat, 12 Sep 2020 06:44:38 -0700 Message-Id: <20200912134441.2407884-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Florian Weimer Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Tunable values and their minimum/maximum values are invisible to users. This patch set adds --list-tunables to ld.so to print tunable values with their minimum and maximum values. For these tunables whose values and minimum/maximum values are determinted at run-time, TUNABLE_SET_ALL and TUNABLE_SET_ALL_FULL are added to update tunable values together with their minimum and maximum values. --list-tunables works on i686 and x86-64. Please test --list-tunables on your native processors. users/hjl/tunable/master branch at: https://gitlab.com/x86-glibc/glibc/-/commits/users/hjl/tunable/master contains the same set of patches. On x86, to make cache info accessible to --list-tunables, they are moved to cpu_features in ld.so and initialized by dummy function pointers via IFUNC relocation. CPU features are initialized by DL_PLATFORM_INIT in dynamic executable and by ARCH_INIT_CPU_FEATURES in static executable. To initialize CPU features when loading ld.so inside of static executable, where DL_PLATFORM_INIT isn't called, CPU features are also initialized by dummy function pointers via IFUNC relocation. $ ./elf/ld.so --list-tunables glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) glibc.elision.skip_lock_after_retries: 3 (min: -2147483648, max: 2147483647) glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0xffffffff) glibc.malloc.perturb: 0 (min: 0, max: 255) glibc.cpu.x86_shared_cache_size: 0x0 (min: 0x0, max: 0xffffffff) glibc.elision.tries: 3 (min: -2147483648, max: 2147483647) glibc.elision.enable: 0 (min: 0, max: 1) glibc.cpu.x86_rep_movsb_threshold: 0x800 (min: 0x100, max: 0xffffffff) glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffff) glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffff) glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffff) glibc.cpu.x86_non_temporal_threshold: 0x0 (min: 0x0, max: 0xffffffff) glibc.cpu.x86_shstk: glibc.cpu.hwcap_mask: 0x1 (min: 0x0, max: 0xffffffff) glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) glibc.elision.skip_trylock_internal_abort: 3 (min: -2147483648, max: 2147483647) glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0xffffffff) glibc.cpu.x86_ibt: glibc.cpu.hwcaps: glibc.elision.skip_lock_internal_abort: 3 (min: -2147483648, max: 2147483647) glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0xffffffff) glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0xffffffff) glibc.cpu.x86_data_cache_size: 0x0 (min: 0x0, max: 0xffffffff) glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0xffffffff) glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0xffffffff) glibc.pthread.mutex_spin_count: 100 (min: 0, max: 32767) glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0xffffffff) glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0xffffffff) glibc.malloc.check: 0 (min: 0, max: 3) H.J. Lu (3): x86: Initialize CPU info via IFUNC relocation [BZ 26203] Set tunable value as well as min/max values ld.so: Add --list-tunables to print tunable values NEWS | 2 + elf/Makefile | 6 +- elf/dl-tunables.c | 53 +- elf/dl-tunables.h | 20 +- elf/rtld.c | 37 +- manual/README.tunables | 24 +- manual/tunables.texi | 37 ++ sysdeps/i386/dl-machine.h | 3 +- sysdeps/x86/cacheinfo.c | 873 ++------------------------- sysdeps/x86/cpu-cacheinfo.c | 922 +++++++++++++++++++++++++++++ sysdeps/x86/cpu-features.c | 25 +- sysdeps/x86/dl-get-cpu-features.c | 25 +- sysdeps/x86/include/cpu-features.h | 23 + sysdeps/x86_64/dl-machine.h | 3 +- 14 files changed, 1201 insertions(+), 852 deletions(-) create mode 100644 sysdeps/x86/cpu-cacheinfo.c