From patchwork Fri Apr 24 12:29:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayshao-oc X-Patchwork-Id: 38865 Return-Path: X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from ZXSHCAS2.zhaoxin.com (unknown [203.148.12.82]) by sourceware.org (Postfix) with ESMTPS id 385D138930F1 for ; Fri, 24 Apr 2020 12:29:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 385D138930F1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Mayshao-oc@zhaoxin.com Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 24 Apr 2020 20:29:41 +0800 Received: from localhost.localdomain (124.64.17.172) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 24 Apr 2020 20:29:39 +0800 From: mayshao-oc To: CC: , , , , , , mayshao-oc Subject: [PATCH v3 0/3] x86: Add support for Zhaoxin processors Date: Fri, 24 Apr 2020 20:29:29 +0800 Message-ID: <1587731372-9324-1-git-send-email-mayshao-oc@zhaoxin.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [124.64.17.172] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx3.zhaoxin.com (10.29.252.165) X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, RCVD_IN_ABUSEAT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Apr 2020 12:29:51 -0000 This patch series fix Shanghai Zhaoxin processor CPU Vendor ID detection problem in glibc sysdep module. Current glibc doesn't recognize Zhaoxin CPU Vendor ID("CentaurHauls" and "Shanghai") and set kind to arch_kind_other. These lead to incorrect result of __cache_sysconf(), incorrect value for variables like __x86_shared_cache_size, and fail of test case tst-get-cpu-features. v3: - code formatting fixups - Add a new function get_common_info() that extracts the code in init_cacheinfo() to get the value of shared, threads. v2: https://sourceware.org/pipermail/libc-alpha/2020-March/112286.html - Remove the bit_arch_Prefer_MAP_32BIT_EXEC flag on the Zhaoxin processor with family==0x6. v1: https://sourceware.org/pipermail/libc-alpha/2019-December/109170.html This series was checked on x86_64-linux-gnu. mayshao (3): x86: Add CPU Vendor ID detection support for Zhaoxin processors x86: Add cache information support for Zhaoxin processors x86: Add the test case of __get_cpu_features support for Zhaoxin processors sysdeps/x86/cacheinfo.c | 477 ++++++++++++++++++++++--------------- sysdeps/x86/cpu-features.c | 54 +++++ sysdeps/x86/cpu-features.h | 1 + sysdeps/x86/tst-get-cpu-features.c | 2 + 4 files changed, 338 insertions(+), 196 deletions(-)