From patchwork Mon Mar 30 05:33:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "May Shao(BJ-RD)" X-Patchwork-Id: 38654 Return-Path: X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from ZXSHCAS1.zhaoxin.com (unknown [203.148.12.81]) by sourceware.org (Postfix) with ESMTPS id D309F385B835 for ; Mon, 30 Mar 2020 05:33:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D309F385B835 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=MayShao@zhaoxin.com Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:52 +0800 Received: from dmdba-HX001EM2.zhaoxin.com (10.29.8.4) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:51 +0800 From: MayShao To: CC: , , , , Subject: [PATCH v2 0/3] x86: Add support for Zhaoxin processors Date: Mon, 30 Mar 2020 13:33:47 +0800 Message-ID: <1585546430-6167-1-git-send-email-MayShao@zhaoxin.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.29.8.4] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx1.zhaoxin.com (10.29.252.163) X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_50, BODY_8BITS, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Mar 2020 05:33:58 -0000 This patch series fix Shanghai Zhaoxin processor CPU Vendor ID detection problem in glibc sysdep module. Current glibc doesn't recognize Zhaoxin CPU Vendor ID("CentaurHauls" and "Shanghai") and set kind to arch_kind_other. These lead to incorrect result of __cache_sysconf(), incorrect value for variables like __x86_shared_cache_size, and fail of test case tst-get-cpu-features. Previous version: https://sourceware.org/pipermail/libc-alpha/2019-December/109170.html More disscussion: https://sourceware.org/pipermail/libc-alpha/2019-December/109227.html Changes from previous version: - Remove the bit_arch_Prefer_MAP_32BIT_EXEC flag on the Zhaoxin processor with family==0x6. This series was tested on x86_64-linux-gnu. MayShao (3): x86: Add CPU Vendor ID detection support for Zhaoxin processors x86: Add cache information support for Zhaoxin processors x86: Add the test cse of __get_cpu_features support for Zhaoxin processors sysdeps/x86/cacheinfo.c | 185 +++++++++++++++++++++++++++++++++++++ sysdeps/x86/cpu-features.c | 58 ++++++++++++ sysdeps/x86/cpu-features.h | 1 + sysdeps/x86/tst-get-cpu-features.c | 2 + 4 files changed, 246 insertions(+) --- 2.7.4 保密声明： 本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited.