From patchwork Wed Jan 29 18:13:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 37612 Received: (qmail 7625 invoked by alias); 29 Jan 2020 18:13:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 7522 invoked by uid 89); 29 Jan 2020 18:13:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=1978, 14519, 2811, probe X-HELO: esa1.hgst.iphmx.com Received: from esa1.hgst.iphmx.com (HELO esa1.hgst.iphmx.com) (68.232.141.245) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Jan 2020 18:13:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1580321596; x=1611857596; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-id:content-transfer-encoding: mime-version; bh=4qeKrtRGoal11CZP2+m+cyZaUI8oMCu5uQPHWbZxE5w=; b=flwrJBNBxVZ2uTV/YY3fXzMoCvmSpTTvueIbdOhbi7rZAaAfeGu1T2uw kipJlKTLJ8N0xzvg0asrjHQOXtLRl8Ls/1gdx5K4JrZahGuY+VcyXO/YM Gw3O+pg8KPmmoN8qymgESps2Yc2PLpNFqX4fnTZkAZvqqYG0K0oZYDC3Q ARzEfXUKXM1ojGAApDo7p075dDfjL7akoi07alWLlI+8sQoHTyePBb0xH 8cZVhhZJkLxFIYDKE+Lcc4vbSG7wkAOXM1b+8E4mW2st4xU/KTBdezFsg loaUs9C0qa6PUmDzn3ivAo0odiidEnr3uuX95jhFryZxT9/XbmE1SH53m w==; IronPort-SDR: WkhEaVXcA+F3p6dLDPuoPUIGL21PIY9n3wh83VxS/tXJ+9NDdqmucydK0IAWfPcbnxNMGZ0ggQ VwElskUwazC32C7TihZfSpkKuTmk1eAxNh5F1DhT33EIUI4NtF5UiRqKwZwmayhnvZUJNTm6nQ LqhHMLe+oT3TWtES/aZc3cHebVFDdIlOBFJEbNBXEtZzhUhcTWE1WZrsAonvc/c8XzuIwGZ4gj 49hKJ9fWQ2emLtJZ9XoRA3vn7/4ygNSDFBhjnmx0eG5/5IFeHewGah7iP8ZrEh+DnREpLF6deT jOM= Received: from mail-dm6nam11lp2171.outbound.protection.outlook.com (HELO NAM11-DM6-obe.outbound.protection.outlook.com) ([104.47.57.171]) by ob1.hgst.iphmx.com with ESMTP; 30 Jan 2020 02:13:14 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=J8qOoKB4/kAyCYGzEpe64HlQzmLZIuGqvPkTg3WZanh4W2jprBhQ3E6ODL/n4CQgy3z6QdWit1rx6JMkVP0SQhoHfZk7kzgqTE3l+kkHtXI8860Ci/maqf5lrE5FUEuDg8LAVxvnMHzlKm0UGEfsr3IE/6xkO52enaE1AhP1u8U2W6U2dwI94Vc66MKqbUtovI5UDA3imS9c31Om49AzbHIQmMjQJT/bJkhpk0qBO0PaebzSVcErJ5JUtj3g0hWLCGYI3a7jenrLeLkU1XBEFs3FxSizA0jyimCOAim5+w7RGrOZZnv1bQtQkOYEz5Yxap5cvbyTjko/gGnongs2lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=m5pS27LUtVl45ZCqERv7st17yAmd7J+F+triTqg05X0=; b=UDX5piZk1x6e7p/BlDFFzqi/FaRk3boJrDvpMf9qCVhwGlYVqMgyVPpJa/T9ey9q17MEtgK7sCuJQzpZNM6BkjsXz/qiY2F7/ZC26nSDCddmMCBvp4otM2OwGE/KgbwCtRkUG1gRwJA6yVV57y+yrrPuWZF77m1gGkr0o+sOUeTg3zVq6cFfpeJ0DBlMOzJH9qv6SRZert04pkXh7cQjAN1AZ2Af/i4iWMhkrQ2PCiyE05p31pxZ+kqb5sIsLvWxAPAodGUQ6sZSaDA+/Js+ISxWF7vrtPyQZkZqw9L9eQrk4oSR4Xvwi1+lFHIMCtfStJqnJkVcg0Itx+h73Iy1uQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=m5pS27LUtVl45ZCqERv7st17yAmd7J+F+triTqg05X0=; b=FOYA/FTDcuTbQy9mrZH6QJ+ukCVJzNMPDp8xAXQ5xiokD5Pfo1Vi5m84Y18iCnIfA0qK0I3LPG51qPkgZeeO1jQLVZZyx7uhh9lYNI46Pcpp517IfrB57LILFAvksZbZ96fzuGufY2nF1eE+qQ0gGGftnE2wrYzDkM33/qk9cVc= Received: from BY5PR04MB6980.namprd04.prod.outlook.com (10.186.134.11) by BY5PR04MB6328.namprd04.prod.outlook.com (52.133.250.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2665.20; Wed, 29 Jan 2020 18:13:13 +0000 Received: from BY5PR04MB6980.namprd04.prod.outlook.com ([fe80::d068:7819:b5cf:353]) by BY5PR04MB6980.namprd04.prod.outlook.com ([fe80::d068:7819:b5cf:353%5]) with mapi id 15.20.2665.027; Wed, 29 Jan 2020 18:13:13 +0000 From: "Maciej W. Rozycki" To: "gdb-patches@sourceware.org" CC: Jim Wilson , Andrew Burgess , Palmer Dabbelt , Tom Tromey , "guoren@kernel.org" , "lifang_xia@c-sky.com" , "yunhai_shang@c-sky.com" , "jiangshuai_li@c-sky.com" Subject: [PATCH v2 1/3] RISC-V/Linux/native: Determine FLEN dynamically Date: Wed, 29 Jan 2020 18:13:13 +0000 Message-ID: References: In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=macro@wdc.com; x-ms-exchange-transport-forked: True wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-messagedata: RCO+pK+Nr0R8VxuUDjKqlPAF8OB6Gv9v58PG2fu1j2N8V11w5aT99TU23CBRjUd5yoT5jGWYJ6wgjI+uWOJr1RJ0U0i0I6ucEByU2QOO8oTCvD7GAdhcfJmBL2ZeyYb7J44ADNJ13PUIugjT7pUg9w== Content-ID: <08567398993D9E4AA6F654C5C8521314@namprd04.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LET1NF+ZkDLc2wuZAJoguEcVTVf/4l3FPd4hbtwy0jDjWCkjB4em1sPXlJrSJKB1 Fix RISC-V native Linux support to handle a 64-bit FPU (FLEN == 64) with both RV32 and RV64 systems, which is a part of the current Linux ABI for hard-float systems, rather than assuming that (FLEN == XLEN) in target description determination and that (FLEN == 64) in register access. We can do better however and not rely on any particular value of FLEN and probe for it dynamically, by observing that the PTRACE_GETREGSET ptrace(2) call will only accept an exact regset size, and that will reflect FLEN. Therefore iterate over the call in target description determination with a geometrically increasing regset size until a match is marked by a successful ptrace(2) call completion or we run beyond the maximum size we can support. Update register accessors accordingly, using FLEN determined to size the buffer used for NT_PRSTATUS requests and then to exchange data with the regcache. Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG, however NFPREG is nowhere defined. gdb/ * riscv-linux-nat.c [!NFPREG] (NFPREG): New macro. (supply_fpregset_regnum, fill_fpregset): Handle regset buffer offsets according to FLEN determined. (riscv_linux_nat_target::read_description): Determine FLEN dynamically. (riscv_linux_nat_target::fetch_registers): Size regset buffer according to FLEN determined. (riscv_linux_nat_target::store_registers): Likewise. --- Hi, I'm not particularly happy with the lengthy lines in `fill_fpregset' and `supply_fpregset_regnum' causing multiple wrapping and deep indentation, but technically there is nothing wrong with it, so I'll leave it to a later clean-up. Maciej Changes from v1: - Also set the size of the regset buffer dynamically in `riscv_linux_nat_target::fetch_registers' and `riscv_linux_nat_target::store_registers', and update `fill_fpregset' and `supply_fpregset_regnum' accordingly. --- gdb/riscv-linux-nat.c | 97 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 75 insertions(+), 22 deletions(-) gdb-riscv-linux-nat-flen.diff Index: binutils-gdb/gdb/riscv-linux-nat.c =================================================================== --- binutils-gdb.orig/gdb/riscv-linux-nat.c +++ binutils-gdb/gdb/riscv-linux-nat.c @@ -28,6 +28,11 @@ #include +/* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ +#ifndef NFPREG +# define NFPREG 33 +#endif + /* RISC-V Linux native additions to the default linux support. */ class riscv_linux_nat_target final : public linux_nat_target @@ -88,21 +93,33 @@ static void supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs, int regnum) { + int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM); + union + { + const prfpregset_t *fpregs; + const gdb_byte *buf; + } + fpbuf = { .fpregs = fpregs }; int i; if (regnum == -1) { /* We only support the FP registers and FCSR here. */ for (i = RISCV_FIRST_FP_REGNUM; i <= RISCV_LAST_FP_REGNUM; i++) - regcache->raw_supply (i, &fpregs->__d.__f[i - RISCV_FIRST_FP_REGNUM]); + regcache->raw_supply (i, + fpbuf.buf + flen * (i - RISCV_FIRST_FP_REGNUM)); - regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); + regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, + fpbuf.buf + flen * (RISCV_LAST_FP_REGNUM + - RISCV_FIRST_FP_REGNUM + 1)); } else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) regcache->raw_supply (regnum, - &fpregs->__d.__f[regnum - RISCV_FIRST_FP_REGNUM]); + fpbuf.buf + flen * (regnum - RISCV_FIRST_FP_REGNUM)); else if (regnum == RISCV_CSR_FCSR_REGNUM) - regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); + regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, + fpbuf.buf + flen * (RISCV_LAST_FP_REGNUM + - RISCV_FIRST_FP_REGNUM + 1)); } /* Copy all floating point registers from regset FPREGS into REGCACHE. */ @@ -145,19 +162,33 @@ void fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs, int regnum) { + int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM); + union + { + prfpregset_t *fpregs; + gdb_byte *buf; + } + fpbuf = { .fpregs = fpregs }; + if (regnum == -1) { /* We only support the FP registers and FCSR here. */ for (int i = RISCV_FIRST_FP_REGNUM; i <= RISCV_LAST_FP_REGNUM; i++) - regcache->raw_collect (i, &fpregs->__d.__f[i - RISCV_FIRST_FP_REGNUM]); + regcache->raw_collect (i, + fpbuf.buf + flen * (i - RISCV_FIRST_FP_REGNUM)); - regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); + regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, + fpbuf.buf + flen * (RISCV_LAST_FP_REGNUM + - RISCV_FIRST_FP_REGNUM + 1)); } else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) regcache->raw_collect (regnum, - &fpregs->__d.__f[regnum - RISCV_FIRST_FP_REGNUM]); + fpbuf.buf + flen * (regnum + - RISCV_FIRST_FP_REGNUM)); else if (regnum == RISCV_CSR_FCSR_REGNUM) - regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); + regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, + fpbuf.buf + flen * (RISCV_LAST_FP_REGNUM + - RISCV_FIRST_FP_REGNUM + 1)); } /* Return a target description for the current target. */ @@ -166,8 +197,8 @@ const struct target_desc * riscv_linux_nat_target::read_description () { struct riscv_gdbarch_features features; - struct iovec iov; elf_fpregset_t regs; + int flen; int tid; /* Figuring out xlen is easy. */ @@ -175,19 +206,39 @@ riscv_linux_nat_target::read_description tid = inferior_ptid.lwp (); - iov.iov_base = ®s; - iov.iov_len = sizeof (regs); + /* Start with no f-registers. */ + features.flen = 0; - /* Can we fetch the f-registers? */ - if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, - (PTRACE_TYPE_ARG3) &iov) == -1) - features.flen = 0; /* No f-registers. */ - else + /* How much worth of f-registers can we fetch if any? */ + for (flen = sizeof (regs.__f.__f[0]); ; flen *= 2) { - /* TODO: We need a way to figure out the actual length of the - f-registers. We could have 64-bit x-registers, with 32-bit - f-registers. For now, just assumed xlen and flen match. */ - features.flen = features.xlen; + size_t regset_size; + struct iovec iov; + + /* Regsets have a uniform slot size, so we count FSCR like an FGR. */ + regset_size = ELF_NFPREG * flen; + if (regset_size > sizeof (regs)) + break; + + iov.iov_base = ®s; + iov.iov_len = regset_size; + if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, + (PTRACE_TYPE_ARG3) &iov) == -1) + { + switch (errno) + { + case EINVAL: + continue; + case EIO: + break; + default: + perror_with_name (_("Couldn't get registers")); + break; + } + } + else + features.flen = flen; + break; } return riscv_create_target_description (features); @@ -228,7 +279,8 @@ riscv_linux_nat_target::fetch_registers elf_fpregset_t regs; iov.iov_base = ®s; - iov.iov_len = sizeof (regs); + iov.iov_len = ELF_NFPREG * register_size (regcache->arch (), + RISCV_FIRST_FP_REGNUM); if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, (PTRACE_TYPE_ARG3) &iov) == -1) @@ -289,7 +341,8 @@ riscv_linux_nat_target::store_registers elf_fpregset_t regs; iov.iov_base = ®s; - iov.iov_len = sizeof (regs); + iov.iov_len = ELF_NFPREG * register_size (regcache->arch (), + RISCV_FIRST_FP_REGNUM); if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, (PTRACE_TYPE_ARG3) &iov) == -1)