diff mbox

[RFC,4/4] gdbserver: Add RISC-V/Linux support

Message ID alpine.LFD.2.21.2001231518180.14118@redsun52.ssa.fujisawa.hgst.com
State Superseded
Headers show

Commit Message

Maciej W. Rozycki Jan. 23, 2020, 7:42 p.m. UTC
Implement RISC-V/Linux support for both RV64 and RV32 systems, including 
XML target description handling based on features determined, GPR and 
FPR regset support including dynamic sizing of the latter, and software 
breakpoint handling.

Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
however NFPREG is nowhere defined.

	gdb/
	* arch/riscv.h (riscv_create_target_description): Remove `const' 
	qualifier from the return type.
	* arch/riscv.c (riscv_create_target_description): Likewise.

	gdb/gdbserver/
	* linux-riscv-low.c: New file.
	* Makefile.in (SFILES): Add linux-riscv-low.c and arch/riscv.c.
	* configure.srv <riscv*-*-linux*> (srv_tgtobj)
	(srv_linux_regsets, srv_linux_usrregs, srv_linux_thread_db): 
	Define.
---
Hi,

 Posted as an RFC as this hits a major issue with GDB rejecting the XML 
description supplied, e.g.:

warning: while parsing target description (at line 4): Target description specified unknown architecture "riscv:rv64id"
warning: Could not load XML target description; ignoring

with HiFive Unleashed; clearly GDB is unhappy with the `riscv:rv64id' 
architecture name produced by its own shared code, and not surprisingly, 
as it only has `riscv', `riscv:rv64' and `riscv:rv32' available to choose 
from as far as RISC-V targets are concerned, as easily verified with:

(gdb) set architecture

As the architecture names come from BFD it will clearly have to be there 
that the problem is fixed, with the ISA suffixes driving the choice of 
instructions handled by the disassembler and possibly other functions.

 Also I think large parts of `riscv_linux_nat_target::read_description' in 
RISC-V/Linux/native support could be factored out to a piece of code 
shared with `riscv_arch_setup'.  This might be less important a problem, 
but nevertheless I think it should be done sooner than later so as not to 
make the two pieces diverge, and a preparatory change inserted ahead of 
this one for this purpose might actually be the best approach.  I have 
planned to do that once the XML target description acceptance problem has 
been fixed.

 I have run initial lp64d multilib remote testing with HiFive Unleashed as 
the target.  Results were as follows:

		=== gdb Summary ===

# of expected passes		58054
# of unexpected failures	621
# of unexpected successes	4
# of expected failures		49
# of unknown successes		5
# of known failures		72
# of unresolved testcases	110
# of untested testcases		100
# of unsupported tests		232

but no further analysis has been made and also they come from Nov 6th 
only, so they may not be up to date with current GDB.  I thought it would 
be more important to get the XML issue fixed first.  Also native gdbserver 
testing should also be done as well as should native reference testing.

 Questions, comments?

  Maciej
---
 gdb/arch/riscv.c                |    2 
 gdb/arch/riscv.h                |    4 
 gdb/gdbserver/Makefile.in       |    2 
 gdb/gdbserver/configure.srv     |    6 
 gdb/gdbserver/linux-riscv-low.c |  300 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 311 insertions(+), 3 deletions(-)

gdb-riscv-gdbserver-linux.diff

Comments

Tom Tromey Jan. 23, 2020, 9:42 p.m. UTC | #1
>>>>> "Maciej" == Maciej W Rozycki <macro@wdc.com> writes:

Maciej> Implement RISC-V/Linux support for both RV64 and RV32 systems, including 
Maciej> XML target description handling based on features determined, GPR and 
Maciej> FPR regset support including dynamic sizing of the latter, and software 
Maciej> breakpoint handling.

I saw a couple of small nits here.

Maciej> Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
Maciej> however NFPREG is nowhere defined.

In case you haven't already, please report this to glibc.

Maciej> As the architecture names come from BFD it will clearly have to be there 
Maciej> that the problem is fixed, with the ISA suffixes driving the choice of 
Maciej> instructions handled by the disassembler and possibly other functions.

Seems reasonable enough.  I don't really know much about this area
though.

Maciej>  Also I think large parts of `riscv_linux_nat_target::read_description' in 
Maciej> RISC-V/Linux/native support could be factored out to a piece of code 
Maciej> shared with `riscv_arch_setup'.  This might be less important a problem, 
Maciej> but nevertheless I think it should be done sooner than later so as not to 
Maciej> make the two pieces diverge

Agreed.

Maciej> +/* Implementation of linux_target_ops method "regs_info".  */
Maciej> +
Maciej> +static const struct regs_info *
Maciej> +riscv_regs_info (void)

We stopped using "(void)" in new code, in favor of just "()".
This showed up in a few spots.

Tom
Jim Wilson Jan. 24, 2020, 1:18 a.m. UTC | #2
On Thu, Jan 23, 2020 at 11:42 AM Maciej W. Rozycki <macro@wdc.com> wrote:
> Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
> however NFPREG is nowhere defined.

I remember that this was discussed on the glibc lists, but I don't
know if a formal bug report was filed.  We unfortunately don't have an
active glibc maintainer, and I'm helping to maintain so much stuff
that I'm not fixing a glibc bug unless it is blocking someone's
progress, and this does not appear to be a blocker for this patch.

>         gdb/
>         * arch/riscv.h (riscv_create_target_description): Remove `const'
>         qualifier from the return type.
>         * arch/riscv.c (riscv_create_target_description): Likewise.
>
>         gdb/gdbserver/
>         * linux-riscv-low.c: New file.
>         * Makefile.in (SFILES): Add linux-riscv-low.c and arch/riscv.c.
>         * configure.srv <riscv*-*-linux*> (srv_tgtobj)
>         (srv_linux_regsets, srv_linux_usrregs, srv_linux_thread_db):
>         Define.

I didn't really review the patch since I've never done any gdbserver
work.  But I did build and test it and it worked for me.  My gdb
testsuite results look roughly the same with and without the patch
set.

I did have to add a missing build_gdbserver=yes line to the
riscv*-*-linux* block in configure.tgt.  I will submit that as a patch
if you don't.

>  Posted as an RFC as this hits a major issue with GDB rejecting the XML
> description supplied, e.g.:
>
> warning: while parsing target description (at line 4): Target description specified unknown architecture "riscv:rv64id"
> warning: Could not load XML target description; ignoring

The problem isn't only in bfd.  gdb/arch/riscv.c
riscv_create_target_description() creates the same kind of strings.
Anyways, this seems to be a simple issue with bfd/cpu-riscv.c using
bfd_default_scan.  It needs to be fixed to use a riscv specific scan
function that ignores trailing characters in the string when they
don't affect the bfd arch match.  I was able to reproduce the problem,
and wrote a bfd patch that is working for me.  This should not be a
blocking factor for the patch, as I can get the bfd patch in tomorrow
or so, unless maybe you want to try it first.

Jim
Maciej W. Rozycki Jan. 24, 2020, 7:08 p.m. UTC | #3
On Thu, 23 Jan 2020, Tom Tromey wrote:

> Maciej> Implement RISC-V/Linux support for both RV64 and RV32 systems, including 
> Maciej> XML target description handling based on features determined, GPR and 
> Maciej> FPR regset support including dynamic sizing of the latter, and software 
> Maciej> breakpoint handling.
> 
> I saw a couple of small nits here.

 Thanks for looking through my proposal!

> Maciej> Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
> Maciej> however NFPREG is nowhere defined.
> 
> In case you haven't already, please report this to glibc.

 Yep, see: <https://sourceware.org/ml/libc-alpha/2019-10/msg00233.html>, 
and the discussion downthread.

> Maciej> +/* Implementation of linux_target_ops method "regs_info".  */
> Maciej> +
> Maciej> +static const struct regs_info *
> Maciej> +riscv_regs_info (void)
> 
> We stopped using "(void)" in new code, in favor of just "()".
> This showed up in a few spots.

 Right, I'm pretty much in the C world still; will fix that in the next 
iteration.

  Maciej
Maciej W. Rozycki Jan. 24, 2020, 7:47 p.m. UTC | #4
On Thu, 23 Jan 2020, Jim Wilson wrote:

> > Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
> > however NFPREG is nowhere defined.
> 
> I remember that this was discussed on the glibc lists, but I don't
> know if a formal bug report was filed.  We unfortunately don't have an
> active glibc maintainer, and I'm helping to maintain so much stuff
> that I'm not fixing a glibc bug unless it is blocking someone's
> progress, and this does not appear to be a blocker for this patch.

 I actually volunteered to become a glibc RISC-V machine maintainer, but 
then I have to admit I haven't been pursuing it particularly actively. :(

> >         gdb/
> >         * arch/riscv.h (riscv_create_target_description): Remove `const'
> >         qualifier from the return type.
> >         * arch/riscv.c (riscv_create_target_description): Likewise.
> >
> >         gdb/gdbserver/
> >         * linux-riscv-low.c: New file.
> >         * Makefile.in (SFILES): Add linux-riscv-low.c and arch/riscv.c.
> >         * configure.srv <riscv*-*-linux*> (srv_tgtobj)
> >         (srv_linux_regsets, srv_linux_usrregs, srv_linux_thread_db):
> >         Define.
> 
> I didn't really review the patch since I've never done any gdbserver
> work.  But I did build and test it and it worked for me.  My gdb
> testsuite results look roughly the same with and without the patch
> set.
> 
> I did have to add a missing build_gdbserver=yes line to the
> riscv*-*-linux* block in configure.tgt.  I will submit that as a patch
> if you don't.

 Indeed, that's useful for a native configuration to build the gdbserver/ 
subdirectory automagically and I missed that, having not looked into it 
(for cross-compilation you need to build `gdbserver' explictly of course).  
Now fixed and included with an updated version, thanks for catching it!

> >  Posted as an RFC as this hits a major issue with GDB rejecting the XML
> > description supplied, e.g.:
> >
> > warning: while parsing target description (at line 4): Target description specified unknown architecture "riscv:rv64id"
> > warning: Could not load XML target description; ignoring
> 
> The problem isn't only in bfd.  gdb/arch/riscv.c
> riscv_create_target_description() creates the same kind of strings.

 Well, that's exactly where `gdbserver' gets its string from.

> Anyways, this seems to be a simple issue with bfd/cpu-riscv.c using
> bfd_default_scan.  It needs to be fixed to use a riscv specific scan
> function that ignores trailing characters in the string when they
> don't affect the bfd arch match.  I was able to reproduce the problem,
> and wrote a bfd patch that is working for me.  This should not be a
> blocking factor for the patch, as I can get the bfd patch in tomorrow
> or so, unless maybe you want to try it first.

 Native regression-testing of 1/4 has now completed successfully, so I'll 
run remote testing now with your patch preapplied and adjustments made to 
4/4.  We'll see how it goes.

  Maciej
diff mbox

Patch

Index: binutils-gdb/gdb/arch/riscv.c
===================================================================
--- binutils-gdb.orig/gdb/arch/riscv.c
+++ binutils-gdb/gdb/arch/riscv.c
@@ -43,7 +43,7 @@  static std::unordered_map<riscv_gdbarch_
 
 /* See arch/riscv.h.  */
 
-const target_desc *
+target_desc *
 riscv_create_target_description (struct riscv_gdbarch_features features)
 {
   /* Have we seen this feature set before?  If we have return the same
Index: binutils-gdb/gdb/arch/riscv.h
===================================================================
--- binutils-gdb.orig/gdb/arch/riscv.h
+++ binutils-gdb/gdb/arch/riscv.h
@@ -69,7 +69,7 @@  struct riscv_gdbarch_features
 /* Create and return a target description that is compatible with
    FEATURES.  */
 
-const target_desc *riscv_create_target_description
-	(struct riscv_gdbarch_features features);
+target_desc *riscv_create_target_description
+  (struct riscv_gdbarch_features features);
 
 #endif /* ARCH_RISCV_H */
Index: binutils-gdb/gdb/gdbserver/Makefile.in
===================================================================
--- binutils-gdb.orig/gdb/gdbserver/Makefile.in
+++ binutils-gdb/gdb/gdbserver/Makefile.in
@@ -177,6 +177,7 @@  SFILES = \
 	$(srcdir)/linux-mips-low.c \
 	$(srcdir)/linux-nios2-low.c \
 	$(srcdir)/linux-ppc-low.c \
+	$(srcdir)/linux-riscv-low.c \
 	$(srcdir)/linux-s390-low.c \
 	$(srcdir)/linux-sh-low.c \
 	$(srcdir)/linux-sparc-low.c \
@@ -203,6 +204,7 @@  SFILES = \
 	$(srcdir)/../arch/arm-get-next-pcs.c \
 	$(srcdir)/../arch/arm-linux.c \
 	$(srcdir)/../arch/ppc-linux-common.c \
+	$(srcdir)/../arch/riscv.c \
 	$(srcdir)/../../gdbsupport/btrace-common.c \
 	$(srcdir)/../../gdbsupport/buffer.c \
 	$(srcdir)/../../gdbsupport/cleanups.c \
Index: binutils-gdb/gdb/gdbserver/configure.srv
===================================================================
--- binutils-gdb.orig/gdb/gdbserver/configure.srv
+++ binutils-gdb/gdb/gdbserver/configure.srv
@@ -267,6 +267,12 @@  case "${target}" in
 			srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu.xml"
 			srv_lynxos=yes
 			;;
+  riscv*-*-linux*)	srv_tgtobj="arch/riscv.o linux-riscv-low.o"
+			srv_tgtobj="${srv_tgtobj} ${srv_linux_obj}"
+			srv_linux_regsets=yes
+			srv_linux_usrregs=yes
+			srv_linux_thread_db=yes
+			;;
   s390*-*-linux*)	srv_regobj="s390-linux32.o"
 			srv_regobj="${srv_regobj} s390-linux32v1.o"
 			srv_regobj="${srv_regobj} s390-linux32v2.o"
Index: binutils-gdb/gdb/gdbserver/linux-riscv-low.c
===================================================================
--- /dev/null
+++ binutils-gdb/gdb/gdbserver/linux-riscv-low.c
@@ -0,0 +1,300 @@ 
+/* GNU/Linux/RISC-V specific low level interface, for the remote server
+   for GDB.
+   Copyright (C) 2020 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "server.h"
+
+#include "gdb_proc_service.h"
+#include "linux-low.h"
+#include "tdesc.h"
+#include "arch/riscv.h"
+#include "elf/common.h"
+#include "nat/gdb_ptrace.h"
+#include "opcode/riscv.h"
+
+#include <sys/uio.h>
+
+/* Work around glibc header breakage causing ELF_NFPREG not to be usable.  */
+#ifndef NFPREG
+# define NFPREG 33
+#endif
+
+/* Implementation of linux_target_ops method "arch_setup".  */
+
+static void
+riscv_arch_setup (void)
+{
+  static const char *expedite_regs[] = { "sp", "pc", NULL };
+  struct riscv_gdbarch_features features;
+  elf_fpregset_t regs;
+  target_desc *tdesc;
+  int flen;
+  int tid;
+
+  /* Figuring out xlen is easy.  */
+  features.xlen = sizeof (elf_greg_t);
+
+  tid = lwpid_of (current_thread);
+
+  /* Start with no f-registers.  */
+  features.flen = 0;
+
+  /* How much worth of f-registers can we fetch if any?  */
+  for (flen = sizeof (regs.__f.__f[0]); ; flen *= 2)
+    {
+      size_t regset_size;
+      struct iovec iov;
+
+      /* Regsets have a uniform slot size, so we count FSCR like an FGR.  */
+      regset_size = ELF_NFPREG * flen;
+      if (regset_size > sizeof (regs))
+	break;
+
+      iov.iov_base = &regs;
+      iov.iov_len = regset_size;
+      if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
+		  (PTRACE_TYPE_ARG3) &iov) == -1)
+	{
+	  switch (errno)
+	    {
+	    case EINVAL:
+	      continue;
+	    case EIO:
+	      break;
+	    default:
+	      perror_with_name (_("Couldn't get registers"));
+	      break;
+	    }
+	}
+      else
+	features.flen = flen;
+      break;
+    }
+
+  tdesc = riscv_create_target_description (features);
+  if (!tdesc->expedite_regs)
+    init_target_desc (tdesc, expedite_regs);
+  current_process ()->tdesc = tdesc;
+}
+
+static void
+riscv_fill_gregset (struct regcache *regcache, void *buf)
+{
+  const struct target_desc *tdesc = regcache->tdesc;
+  elf_gregset_t *regset = (elf_gregset_t *) buf;
+  int regno = find_regno (tdesc, "zero");
+  int i;
+
+  collect_register_by_name (regcache, "pc", *regset);
+  for (i = 1; i < ARRAY_SIZE (*regset); i++)
+    collect_register (regcache, regno + i, *regset + i);
+}
+
+static void
+riscv_store_gregset (struct regcache *regcache, const void *buf)
+{
+  const elf_gregset_t *regset = (const elf_gregset_t *) buf;
+  const struct target_desc *tdesc = regcache->tdesc;
+  int regno = find_regno (tdesc, "zero");
+  int i;
+
+  supply_register_by_name (regcache, "pc", *regset);
+  supply_register_zeroed (regcache, regno);
+  for (i = 1; i < ARRAY_SIZE (*regset); i++)
+    supply_register (regcache, regno + i, *regset + i);
+}
+
+static void
+riscv_fill_fpregset (struct regcache *regcache, void *buf)
+{
+  const struct target_desc *tdesc = regcache->tdesc;
+  elf_fpregset_t *regset = (elf_fpregset_t *) buf;
+  int regno = find_regno (tdesc, "ft0");
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (regset->__d.__f); i++)
+    collect_register (regcache, regno + i, regset->__d.__f + i);
+  collect_register_by_name (regcache, "fcsr", &regset->__d.__fcsr);
+}
+
+static void
+riscv_store_fpregset (struct regcache *regcache, const void *buf)
+{
+  const elf_fpregset_t *regset = (const elf_fpregset_t *) buf;
+  const struct target_desc *tdesc = regcache->tdesc;
+  int regno = find_regno (tdesc, "ft0");
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (regset->__d.__f); i++)
+    supply_register (regcache, regno + i, regset->__d.__f + i);
+  supply_register_by_name (regcache, "fcsr", &regset->__d.__fcsr);
+}
+
+static struct regset_info riscv_regsets[] = {
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
+    sizeof (elf_gregset_t), GENERAL_REGS,
+    riscv_fill_gregset, riscv_store_gregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
+    sizeof (elf_fpregset_t), FP_REGS,
+    riscv_fill_fpregset, riscv_store_fpregset },
+  NULL_REGSET
+};
+
+static struct regsets_info riscv_regsets_info =
+  {
+    riscv_regsets, /* regsets */
+    0, /* num_regsets */
+    NULL, /* disabled_regsets */
+  };
+
+static struct regs_info riscv_regs =
+  {
+    NULL, /* regset_bitmap */
+    NULL, /* usrregs */
+    &riscv_regsets_info,
+  };
+
+/* Implementation of linux_target_ops method "regs_info".  */
+
+static const struct regs_info *
+riscv_regs_info (void)
+{
+  return &riscv_regs;
+}
+
+/* Implementation of linux_target_ops method "fetch_register".  */
+
+static int
+riscv_fetch_register (struct regcache *regcache, int regno)
+{
+  const struct target_desc *tdesc = regcache->tdesc;
+
+  if (regno != find_regno (tdesc, "zero"))
+    return 0;
+  supply_register_zeroed (regcache, regno);
+  return 1;
+}
+
+/* Implementation of linux_target_ops method "get_pc".  */
+
+static CORE_ADDR
+riscv_get_pc (struct regcache *regcache)
+{
+  elf_gregset_t regset;
+
+  if (sizeof (regset[0]) == 8)
+    return linux_get_pc_64bit (regcache);
+  else
+    return linux_get_pc_32bit (regcache);
+}
+
+/* Implementation of linux_target_ops method "set_pc".  */
+
+static void
+riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc)
+{
+  elf_gregset_t regset;
+
+  if (sizeof (regset[0]) == 8)
+    linux_set_pc_64bit (regcache, newpc);
+  else
+    linux_set_pc_32bit (regcache, newpc);
+}
+
+/* Correct in either endianness.  */
+static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 };
+static const uint16_t riscv_cbreakpoint = 0x9002;
+
+/* Implementation of linux_target_ops method "breakpoint_kind_from_pc".  */
+
+static int
+riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
+{
+  union
+    {
+      gdb_byte bytes[2];
+      uint16_t insn;
+    }
+  buf;
+
+  if (target_read_memory (*pcptr, buf.bytes, sizeof (buf.insn)) == 0
+      && riscv_insn_length (buf.insn == sizeof (riscv_ibreakpoint)))
+    return sizeof (riscv_ibreakpoint);
+  else
+    return sizeof (riscv_cbreakpoint);
+}
+
+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
+
+static const gdb_byte *
+riscv_sw_breakpoint_from_kind (int kind, int *size)
+{
+  *size = kind;
+  switch (kind)
+    {
+      case sizeof (riscv_ibreakpoint):
+	return (const gdb_byte *) &riscv_ibreakpoint;
+      default:
+	return (const gdb_byte *) &riscv_cbreakpoint;
+    }
+}
+
+/* Implementation of linux_target_ops method "breakpoint_at".  */
+
+static int
+riscv_breakpoint_at (CORE_ADDR pc)
+{
+  union
+    {
+      gdb_byte bytes[2];
+      uint16_t insn;
+    }
+  buf;
+
+  if (target_read_memory (pc, buf.bytes, sizeof (buf.insn)) == 0
+      && (buf.insn == riscv_cbreakpoint
+	  || (buf.insn == riscv_ibreakpoint[0]
+	      && target_read_memory (pc + sizeof (buf.insn), buf.bytes,
+				     sizeof (buf.insn)) == 0
+	      && buf.insn == riscv_ibreakpoint[1])))
+    return 1;
+  else
+    return 0;
+}
+
+struct linux_target_ops the_low_target =
+{
+  riscv_arch_setup,
+  riscv_regs_info,
+  NULL, /* cannot_fetch_register */
+  NULL, /* cannot_store_register */
+  riscv_fetch_register,
+  riscv_get_pc,
+  riscv_set_pc,
+  riscv_breakpoint_kind_from_pc,
+  riscv_sw_breakpoint_from_kind,
+  NULL, /* get_next_pcs */
+  0,    /* decr_pc_after_break */
+  riscv_breakpoint_at,
+};
+
+void
+initialize_low_arch (void)
+{
+  initialize_regsets_info (&riscv_regsets_info);
+}