From patchwork Tue May 22 00:54:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 27384 Received: (qmail 64879 invoked by alias); 22 May 2018 00:54:30 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 64325 invoked by uid 89); 22 May 2018 00:54:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.2 spammy=Connection X-HELO: 9pmail.ess.barracuda.com Received: from 9pmail.ess.barracuda.com (HELO 9pmail.ess.barracuda.com) (64.235.150.225) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 May 2018 00:54:27 +0000 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Tue, 22 May 2018 00:54:12 +0000 Received: from [10.20.78.154] (10.20.78.154) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Mon, 21 May 2018 17:54:13 -0700 Date: Tue, 22 May 2018 01:54:02 +0100 From: "Maciej W. Rozycki" To: Subject: [committed] MIPS/Linux: Disable n32 USR `ptrace' accesses to 64-bit registers Message-ID: User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1526950452-298552-30477-11031-1 X-BESS-VER: 2018.6-r1805181819 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.193230 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 On the MIPS target DSP ASE registers can only be accessed with the PTRACE_PEEKUSR and PTRACE_POKEUSR `ptrace' requests. With the n32 ABI these requests only pass 32-bit data quantities, which are narrower than the width of DSP accumulator registers, which are 64-bit. Generic code is prepared to transfer registers wider than the `ptrace' data type by offsetting into the USR address space, by the data width transferred. That however does not work with the MIPS target, because of how the API has been defined, where USR register addresses are actually indices rather than offsets. Consequently given address `a' using `a + 4' accesses the fourth next register rather than the upper half of the original register. With native debugging this causes clobbered register contents, as well as access failures as locations beyond the available USR space are addressed: (gdb) info registers zero at v0 v1 R0 0000000000000000 0000000000000001 0000000000000001 0000000000000000 a0 a1 a2 a3 R4 0000000010019158 0000000000000000 0000000000000011 0000000010019160 a4 a5 a6 a7 R8 0000000010019160 fffffffffff00000 fffffffffffffff8 0000000000000000 t0 t1 t2 t3 R12 0000000010019150 0000000000000001 0000000000000001 000000000000000f s0 s1 s2 s3 R16 0000000077ee6f20 0000000010007bb0 0000000000000000 0000000000000000 s4 s5 s6 s7 R20 000000000052e668 000000000052f008 0000000000000000 0000000000000000 t8 t9 k0 k1 R24 0000000000000001 0000000010019010 0000000000000000 0000000000000000 gp sp s8 ra R28 0000000010020280 000000007fff4c10 000000007fff4c10 0000000010004f48 status lo hi badvaddr 0000000000109cf3 0000000000943efe 000000000000000e 000000001001900c cause pc 0000000000800024 0000000010004f48 fcsr fir hi1 lo1 0e800000 00f30000 0000000004040404 0101010105050505 hi2 lo2 hi3 lo3 0202020255aa33cc Couldn't read register (#75): Input/output error. (gdb) With `gdbserver' this makes debugging impossible due to a fatal failure: (gdb) target remote :2346 Remote debugging using :2346 Reading symbols from .../sysroot/mips-r2-hard/lib32/ld.so.1...done. 0x77fc3d50 in __start () from .../sysroot/mips-r2-hard/lib32/ld.so.1 (gdb) continue Continuing. warning: Remote failure reply: E01 Remote communication error. Target disconnected.: Connection reset by peer. (gdb) Correct the problem by marking any register in the MIPS backend whose width exceeds the width of the `ptrace' data type unavailable for the purpose of PTRACE_PEEKUSR and PTRACE_POKEUSR requests: (gdb) info registers zero at v0 v1 R0 0000000000000000 0000000000000001 0000000000000001 0000000000000000 a0 a1 a2 a3 R4 0000000010019158 0000000000000000 0000000000000011 0000000010019160 a4 a5 a6 a7 R8 0000000010019160 fffffffffff00000 fffffffffffffff8 0000000000000000 t0 t1 t2 t3 R12 0000000010019150 0000000000000001 0000000000000001 000000000000000f s0 s1 s2 s3 R16 0000000077ee6f20 0000000010007bb0 0000000000000000 0000000000000000 s4 s5 s6 s7 R20 000000000052e5c8 000000000052f008 0000000000000000 0000000000000000 t8 t9 k0 k1 R24 0000000000000001 0000000010019010 0000000000000000 0000000000000000 gp sp s8 ra R28 0000000010020280 000000007fff4be0 000000007fff4be0 0000000010004f48 status lo hi badvaddr 0000000000109cf3 0000000000943efe 000000000000000e 000000001001900c cause pc 0000000000800024 0000000010004f48 fcsr fir hi1 lo1 0e800000 00f30000 hi2 lo2 hi3 lo3 dspctl restart 55aa33cc 0000000000000000 (gdb) as there is no way to access full contents of these registers with the limited API available anyway. This obviously does not affect general-purpose registers (which use the PTRACE_GETREGS and PTRACE_SETREGS requests for access) or floating-point general registers (which use PTRACE_GETFPREGS and PTRACE_SETFPREGS). And $dspctl, being 32-bit, remains accessible too, which is important for BPOSGE32 branch decoding in single-stepping. For DSP accumulator access with the n32 ABI a new `ptrace' API is required on the kernel side. gdb/ * mips-linux-nat.c (mips64_linux_register_addr): Return -1 if the width of the requested register exceeds the width of the `ptrace' data type. gdb/gdbserver/ * linux-mips-low.c (mips_cannot_fetch_register): Return 1 if the width of the requested register exceeds the width of the `ptrace' data type. (mips_cannot_store_register): Likewise. --- Hi, A kernel `ptrace' API update has been posted: Once that has been accepted the GDB side can be updated accordingly, and DSP register state handling also added to core file support. No native or native-gdbserver regressions across the three MIPS ABIs. Committed. Maciej --- gdb/gdbserver/linux-mips-low.c | 8 ++++++++ gdb/mips-linux-nat.c | 5 +++++ 2 files changed, 13 insertions(+) gdb-mips-n32-dsp-disable.diff Index: binutils/gdb/gdbserver/linux-mips-low.c =================================================================== --- binutils.orig/gdb/gdbserver/linux-mips-low.c 2018-02-23 14:14:24.000000000 +0000 +++ binutils/gdb/gdbserver/linux-mips-low.c 2018-05-18 02:39:22.987236110 +0100 @@ -211,6 +211,10 @@ mips_cannot_fetch_register (int regno) tdesc = current_process ()->tdesc; + /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ + if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) + return 1; + if (find_regno (tdesc, "r0") == regno) return 1; @@ -227,6 +231,10 @@ mips_cannot_store_register (int regno) tdesc = current_process ()->tdesc; + /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ + if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) + return 1; + if (find_regno (tdesc, "r0") == regno) return 1; Index: binutils/gdb/mips-linux-nat.c =================================================================== --- binutils.orig/gdb/mips-linux-nat.c 2018-05-17 17:25:26.000000000 +0100 +++ binutils/gdb/mips-linux-nat.c 2018-05-18 02:54:39.440985218 +0100 @@ -145,6 +145,11 @@ mips64_linux_register_addr (struct gdbar if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) error (_("Bogon register number %d."), regno); + /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR + or PTRACE_POKEUSR. */ + if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET)) + return (CORE_ADDR) -1; + if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) regaddr = regno; else if ((regno >= mips_regnum (gdbarch)->fp0)