diff mbox

[committed] mips-tdep: Make FCRs always 32-bit

Message ID alpine.DEB.2.00.1610041425140.11928@tp.orcam.me.uk
State Committed
Headers show

Commit Message

Maciej W. Rozycki Oct. 6, 2016, 4:02 p.m. UTC
Fix a regression from commit f8b73d13b7ca ("Target-described register 
support for MIPS"), 
<https://sourceware.org/ml/gdb-patches/2007-05/msg00340.html>, 
<https://sourceware.org/ml/gdb-patches/2007-06/msg00256.html>, which 
caused Floating Point Control Registers (FCRs) to be shown as 64-bit 
with 64-bit targets.

This came from the legacy register format where all raw registers 
matched the width of the architecture regardless of their actual size.  
The correct size was then set in `mips_register_type' for cooked 
registers presented to the user, which in the case of FCRs meant the 
cooked size was always forced to 32 bits, reflecting their actual 
hardware size, even though the raw format carried them in 64-bit 
quantities on 64-bit targets.  The upper 32 bits carried in the raw FCR 
format have always been don't-cares, not actually retrieved from 
hardware and never written back.

With the introduction of XML register descriptions the layout of 
previously defined raw registers has been preserved, so as to keep 
existing register handling code unchanged and make it easier for GDB and 
`gdbserver' to interact with each other whether neither, either or both 
parties talking over RSP support XML register descriptions.  For the 
XML-described case however `mips_register_type' is not used in raw to 
cooked register conversion, so any special cases coded there are not 
taken into account.

Instead a new function, `mips_pseudo_register_type', has been introduced 
to handle size conversion, however lacking the special case for FCRs for 
the Linux and the now defunct IRIX target.  The correct size has been 
maintained for embedded targets however, due to the bundling of FCRs 
with the embedded registers under the `rawnum >= MIPS_EMBED_FP0_REGNUM + 
32' condition.

Add the missing case to `mips_pseudo_register_type' then, referring to 
the FCR indices explicitly, and observing that between 
`MIPS_EMBED_FP0_REGNUM + 32' and `MIPS_FIRST_EMBED_REGNUM' there is an 
unused register slot whose contents are ignored so with the removal of 
embedded FCRs from under that condition we don't have to care about it 
and we can refer to the embedded registers starting from 
MIPS_FIRST_EMBED_REGNUM instead.

Add a test case too so that we have means to check automatically that 
the correct user-visible size of FCRs is maintained.

	gdb/
	* mips-tdep.c (mips_pseudo_register_type): Make FCRs always 
	32-bit.

	gdb/testsuite/
	* gdb.arch/mips-fcr.exp: New test.
	* gdb.arch/mips-fcr.c: Source for the new test.
---
 No regressions in `mips-mti-linux-gnu' `gdbserver' testing with o32 and 
n64 targets; also smoke-tested with native GDB.  Committed.

  Maciej

gdb-mips-fcr-32bit.diff
diff mbox

Patch

Index: binutils/gdb/mips-tdep.c
===================================================================
--- binutils.orig/gdb/mips-tdep.c	2016-10-05 12:39:53.201531785 +0100
+++ binutils/gdb/mips-tdep.c	2016-10-05 16:42:09.605221651 +0100
@@ -1079,6 +1079,13 @@  mips_pseudo_register_type (struct gdbarc
   if (mips_float_register_p (gdbarch, rawnum))
     return rawtype;
 
+  /* Floating-point control registers are always 32-bit even though for
+     backwards compatibility reasons 64-bit targets will transfer them
+     as 64-bit quantities even if using XML descriptions.  */
+  if (rawnum == mips_regnum (gdbarch)->fp_control_status
+      || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
+    return builtin_type (gdbarch)->builtin_int32;
+
   /* Use pointer types for registers if we can.  For n32 we can not,
      since we do not have a 64-bit pointer type.  */
   if (mips_abi_regsize (gdbarch)
@@ -1111,7 +1118,7 @@  mips_pseudo_register_type (struct gdbarc
      with the displayed type.  */
   if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
       && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
-      && rawnum >= MIPS_EMBED_FP0_REGNUM + 32
+      && rawnum >= MIPS_FIRST_EMBED_REGNUM
       && rawnum <= MIPS_LAST_EMBED_REGNUM)
     return builtin_type (gdbarch)->builtin_int32;
 
Index: binutils/gdb/testsuite/gdb.arch/mips-fcr.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ binutils/gdb/testsuite/gdb.arch/mips-fcr.c	2016-10-06 15:25:53.267176142 +0100
@@ -0,0 +1,22 @@ 
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2016 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+int
+main (void)
+{
+  return 0;
+}
Index: binutils/gdb/testsuite/gdb.arch/mips-fcr.exp
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ binutils/gdb/testsuite/gdb.arch/mips-fcr.exp	2016-10-06 16:00:33.951585374 +0100
@@ -0,0 +1,54 @@ 
+# Copyright (C) 2016 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Contributed by Imagination Technologies, written by Maciej W. Rozycki.
+
+# Test MIPS Floating Point Control Register handling.
+
+if { ![istarget "mips*-*-*"] } then {
+    verbose "Skipping MIPS Floating Point Control Register tests."
+    return
+}
+
+standard_testfile
+
+if { [prepare_for_testing ${testfile}.exp ${testfile}] } {
+    return
+}
+
+if ![runto_main] {
+    return
+}
+
+# First check if we have an FPU available in the first place.
+gdb_test_multiple "show mipsfpu" "check for MIPS floating-point coprocessor" {
+    -re "The MIPS floating-point coprocessor .*\(absent\|unknown\).*$gdb_prompt $" {
+	unsupported "no MIPS floating-point coprocessor in the processor"
+	return
+    }
+    -re "The MIPS floating-point coprocessor .*$gdb_prompt $" {
+	verbose "MIPS floating-point coprocessor check successful."
+    }
+    default {
+	fail
+	return
+    }
+}
+
+# Now check that FCRs are accessible and 32-bit wide.
+gdb_test "info registers \$fcsr" "fcsr: $hex"
+gdb_test "print sizeof \$fcsr" "\\\$$decimal = 4"
+gdb_test "info registers \$fir" "fir: $hex"
+gdb_test "print sizeof \$fir" "\\\$$decimal = 4"