diff mbox

Add micromips support to the MIPS simulator

Message ID alpine.DEB.2.00.1601121840430.5958@tp.orcam.me.uk
State Superseded
Headers show

Commit Message

Maciej W. Rozycki Jan. 12, 2016, 11:01 p.m. UTC
Andrew,

On Fri, 25 Sep 2015, Andrew Bennett wrote:

> This has now been committed.  Once I did the committing I realised that
> I only have Binutils write access permissions.  Is this ok, or do I need
> to get GDB write access as well?

 While investigating PR 18964 I noticed your change (commit 8e394ffc) 
broke building for the mips-linux-gnu target, which does not enable the 
microMIPS instruction set:

gcc -DHAVE_CONFIG_H     -DPROFILE=1 -DWITH_PROFILE=-1  -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 -DWITH_DEFAULT_TARGET_BYTE_ORDER=BFD_ENDIAN_BIG  -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=32 -DWITH_HW=0    -DWITH_RESERVED_BITS=1  -DWITH_SMP=0  -Wall -Wdeclaration-after-statement -Wpointer-arith -Wpointer-sign -Wno-unused -Wunused-value -Wunused-function -Wno-switch -Wno-char-subscripts -Wmissing-prototypes -Wdeclaration-after-statement -Wold-style-definition -Wformat-nonliteral    -DMIPS_MACH_DEFAULT=bfd_mach_mips8000   -I. -I.../sim/mips -I../common -I.../sim/mips/../common -I../../include -I.../sim/mips/../..//include -I../../bfd -I.../sim/mips/../..//bfd -I../../opcodes -I.../sim/mips/../..//opcodes  -pipe -O0 -g  -o run \
          nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a  ../../libiberty/libiberty.a -lm -ldl -lnsl  -L../../zlib -lz
libsim.a(engine.o): In function `delayslot_micromips':
.../sim/mips/micromips.igen:49: undefined reference to `micromips_instruction_decode'
libsim.a(semantics.o): In function `delayslot_micromips':
.../sim/mips/micromips.igen:49: undefined reference to `micromips_instruction_decode'
libsim.a(idecode.o): In function `delayslot_micromips':
.../sim/mips/micromips.igen:49: undefined reference to `micromips_instruction_decode'
collect2: ld returned 1 exit status
make[2]: *** [run] Error 1

As a microMIPS engine is not included in a mips-linux-gnu build the file 
supposed to provide `micromips_instruction_decode' is not generated or 
compiled, whereas `delayslot_micromips' (and a bunch of other functions) 
is built unconditionally.

 Restricting the affected functions to microMIPS processors only has fixed 
the build problem for me, see the patch below.  I have not verified it 
further though, will you be able to look into it soon?

	sim/mips/
	* micromips.igen (delayslot_micromips): Enable for `micromips32',
	`micromips64' and `micromipsdsp' only.
	(process_isa_mode): Enable for `micromips32' and `micromips64'
	only.
	(do_micromips_jalr, do_micromips_jal): Likewise.
	(compute_movep_src_reg): Likewise.
	(compute_andi16_imm): Likewise.
	(convert_fmt_micromips): Likewise.
	(convert_fmt_micromips_cvt_d): Likewise.
	(convert_fmt_micromips_cvt_s): Likewise.

  Maciej

sim-umips-function-proc.diff
diff mbox

Patch

Index: gdb/sim/mips/micromips.igen
===================================================================
--- gdb.orig/sim/mips/micromips.igen	2016-01-12 22:29:38.000000000 +0000
+++ gdb/sim/mips/micromips.igen	2016-01-12 22:37:35.169972819 +0000
@@ -39,6 +39,9 @@ 
 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
 
 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
+*micromipsdsp:
 {
   instruction_word delay_insn;
   sim_events_slip (SD, 1);
@@ -52,12 +55,16 @@ 
 }
 
 :function:::address_word:process_isa_mode:address_word target
+*micromips32:
+*micromips64:
 {
   SD->isa_mode = target & 0x1;
   return (target & (-(1 << 1)));
 }
 
 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return (process_isa_mode (SD_,
@@ -65,6 +72,8 @@ 
 }
 
 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
@@ -72,6 +81,8 @@ 
 
 
 :function:::unsigned32:compute_movep_src_reg:int reg
+*micromips32:
+*micromips64:
 {
   switch(reg)
     {
@@ -88,6 +99,8 @@ 
 }
 
 :function:::unsigned32:compute_andi16_imm:int encoded_imm
+*micromips32:
+*micromips64:
 {
   switch (encoded_imm)
     {
@@ -112,6 +125,8 @@ 
 }
 
 :function:::FP_formats:convert_fmt_micromips:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -123,6 +138,8 @@ 
 }
 
 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -135,6 +152,8 @@ 
 
 
 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {