From patchwork Wed Aug 3 10:56:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fredrik Hederstierna X-Patchwork-Id: 14275 Received: (qmail 122245 invoked by alias); 3 Aug 2016 10:56:41 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 122218 invoked by uid 89); 3 Aug 2016 10:56:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, SPF_PASS autolearn=ham version=3.3.2 spammy=5267, PCs, H*x:Build, v6m X-HELO: mail2.securitas-direct.com Received: from mail2.securitas-direct.com (HELO mail2.securitas-direct.com) (195.170.189.96) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 03 Aug 2016 10:56:28 +0000 Received: from mail.securitas-direct.com (unknown [91.199.64.45]) by Websense Email with ESMTPS id F4008936735B6 for ; Wed, 3 Aug 2016 12:56:24 +0200 (CEST) Received: from smtp.notes.na.collabserv.com ([192.155.248.74]) by mail.securitas-direct.com with ESMTP; 03 Aug 2016 12:56:25 +0200 Received: from localhost by smtp.notes.na.collabserv.com with smtp.notes.na.collabserv.com ESMTP for from ; Wed, 3 Aug 2016 10:56:12 -0000 Received: from us1a3-smtp02.a3.dal06.isc4sb.com (10.106.154.159) by smtp.notes.na.collabserv.com (10.106.227.92) with smtp.notes.na.collabserv.com ESMTP; Wed, 3 Aug 2016 10:56:11 -0000 X-IBM-Helo: us1a3-smtp02.a3.dal06.isc4sb.com X-IBM-MailFrom: fredrik.hederstierna@verisure.com X-IBM-RcptTo: qiyaoltc@gmail.com;gdb-patches@sourceware.org Received: from us1a3-mail13.a3.dal06.isc4sb.com ([10.146.77.97]) by us1a3-smtp02.a3.dal06.isc4sb.com with ESMTP id 2016080310561086-155935 ; Wed, 3 Aug 2016 10:56:10 +0000 MIME-Version: 1.0 Sensitivity: In-Reply-To: <864m73dutq.fsf@gmail.com> References: <864m73dutq.fsf@gmail.com>, <868twkekf1.fsf@gmail.com> Subject: Re: [PATCH] Fix exception unwinding for ARM Cortex-M From: "Fredrik Hederstierna" To: Yao Qi Cc: gdb-patches@sourceware.org Date: Wed, 3 Aug 2016 10:56:11 +0000 X-LLNOutbound: False X-TNEFEvaluated: 1 x-cbid: 16080310-7581-0000-0000-0000003CF2FA X-IBM-ISS-SpamDetectors: Score=0.40962; BY=0; FL=0; FP=0; FZ=0; HX=0; KW=0; PH=0; SC=0.40962; ST=0; TS=0; UL=0; ISC= X-IBM-ISS-DetailInfo: BY=3.00005546; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000177; SDB=6.00739372; UDB=6.00347609; UTC=2016-08-03 10:56:12 x-cbparentid: 16080310-7582-0000-0000-0000008BC18C Message-Id: Hi Yao, thanks for reviewing, I attach here updated patch. I have FSF assignment papers for GCC from December 2005, maybe needs separate assignment for GDB, so I have now sent in application to FSF for GDB assignment as well. gdb/ChangeLog: 2016-08-03 Fredrik Hederstierna * arm-tdep.c (arm_m_addr_is_magic): New function. (arm_addr_bits_remove) (arm_m_exception_unwind_sniffer): Check correct EXC_RETURN values. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index d2661cb..1d154cc 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -464,6 +464,61 @@ arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) return 0; } +/* Determine if the address specified equals any of + these magic return values, called EXC_RETURN, defined + by the ARM v6-M and v7-M architectures. + + From ARMv6-M Reference Manual B1.5.8 + Table B1-5 Exception return behavior + + EXC_RETURN Return To Return Stack + 0xFFFFFFF1 Handler mode Main + 0xFFFFFFF9 Thread mode Main + 0xFFFFFFFD Thread mode Process + + From ARMv7-M Reference Manual B1.5.8 + Table B1-8 EXC_RETURN definition of exception return behavior, no FP + + EXC_RETURN Return To Return Stack + 0xFFFFFFF1 Handler mode Main + 0xFFFFFFF9 Thread mode Main + 0xFFFFFFFD Thread mode Process + + Table B1-9 EXC_RETURN definition of exception return behavior, with FP + + EXC_RETURN Return To Return Stack Frame Type + 0xFFFFFFE1 Handler mode Main Extended + 0xFFFFFFE9 Thread mode Main Extended + 0xFFFFFFED Thread mode Process Extended + 0xFFFFFFF1 Handler mode Main Basic + 0xFFFFFFF9 Thread mode Main Basic + 0xFFFFFFFD Thread mode Process Basic + + For more details see "B1.5.8 Exception return behavior" + in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */ + +static int +arm_m_addr_is_magic (CORE_ADDR addr) +{ + switch (addr) + { + /* Values from Tables in B1.5.8 the EXC_RETURN definitions of + the exception return behavior. */ + case 0xffffffe1: + case 0xffffffe9: + case 0xffffffed: + case 0xfffffff1: + case 0xfffffff9: + case 0xfffffffd: + /* Address is magic. */ + return 1; + + default: + /* Address is not magic. */ + return 0; + } +} + /* Remove useless bits from addresses in a running program. */ static CORE_ADDR arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) @@ -471,7 +526,7 @@ arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) /* On M-profile devices, do not strip the low bit from EXC_RETURN (the magic exception return address). */ if (gdbarch_tdep (gdbarch)->is_m - && (val & 0xfffffff0) == 0xfffffff0) + && arm_m_addr_is_magic (val)) return val; if (arm_apcs_32) @@ -2990,14 +3045,8 @@ arm_m_exception_unwind_sniffer (const struct frame_unwind *self, /* No need to check is_m; this sniffer is only registered for M-profile architectures. */ - /* Exception frames return to one of these magic PCs. Other values - are not defined as of v7-M. See details in "B1.5.8 Exception - return behavior" in "ARMv7-M Architecture Reference Manual". */ - if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9 - || this_pc == 0xfffffffd) - return 1; - - return 0; + /* Check if exception frame returns to a magic PC value. */ + return arm_m_addr_is_magic (this_pc); } /* Frame unwinder for M-profile exceptions. */