From patchwork Thu Apr 6 12:49:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 19880 Received: (qmail 18661 invoked by alias); 6 Apr 2017 12:49:18 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 17032 invoked by uid 89); 6 Apr 2017 12:49:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, MIME_BASE64_BLANKS, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=mod X-HELO: EUR03-AM5-obe.outbound.protection.outlook.com Received: from mail-eopbgr30043.outbound.protection.outlook.com (HELO EUR03-AM5-obe.outbound.protection.outlook.com) (40.107.3.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 06 Apr 2017 12:49:13 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com (10.160.211.19) by AM3PR08MB0104.eurprd08.prod.outlook.com (10.160.211.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1005.10; Thu, 6 Apr 2017 12:49:10 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::5931:f431:f97d:943d]) by AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::5931:f431:f97d:943d%16]) with mapi id 15.01.1005.021; Thu, 6 Apr 2017 12:49:10 +0000 From: Alan Hayward To: Yao Qi CC: "gdb-patches@sourceware.org" , nd Subject: Re: [PATCH 10/11] Add XTENSA_MAX_REGISTER_SIZE Date: Thu, 6 Apr 2017 12:49:10 +0000 Message-ID: References: <86y3vfp308.fsf@gmail.com> In-Reply-To: <86y3vfp308.fsf@gmail.com> authentication-results: gmail.com; dkim=none (message not signed) header.d=none; gmail.com; dmarc=none action=none header.from=arm.com; x-ms-exchange-messagesentrepresentingtype: 1 x-microsoft-exchange-diagnostics: 1; AM3PR08MB0104; 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SRVR:AM3PR08MB0104; BCL:0; PCL:0; RULEID:; SRVR:AM3PR08MB0104; x-forefront-prvs: 02698DF457 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39410400002)(39860400002)(39840400002)(39850400002)(39450400003)(39400400002)(377424004)(24454002)(6506006)(82746002)(3660700001)(5250100002)(36756003)(2906002)(86362001)(6486002)(83716003)(305945005)(6246003)(39060400002)(4326008)(3280700002)(7736002)(229853002)(25786009)(6916009)(99286003)(1411001)(66066001)(6436002)(8676002)(53546009)(38730400002)(6116002)(6512007)(110136004)(54356999)(50986999)(76176999)(54906002)(189998001)(5660300001)(53936002)(3846002)(2900100001)(102836003)(81166006)(33656002)(2950100002)(8936002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0104; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:ovrnspm; PTR:InfoNoRecords; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2017 12:49:10.2113 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0104 > On 5 Apr 2017, at 11:23, Yao Qi wrote: > > Alan Hayward writes: > >> @@ -559,7 +559,7 @@ xtensa_pseudo_register_read (struct gdbarch *gdbarch, >> && (regnum >= gdbarch_tdep (gdbarch)->a0_base) >> && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) >> { >> - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); >> + gdb_byte *buf = (gdb_byte *) alloca (XTENSA_MAX_REGISTER_SIZE); >> enum register_status status; >> >> status = regcache_raw_read (regcache, >> @@ -655,7 +655,7 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch, >> && (regnum >= gdbarch_tdep (gdbarch)->a0_base) >> && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) >> { >> - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); >> + gdb_byte *buf = (gdb_byte *) alloca (XTENSA_MAX_REGISTER_SIZE); >> >> regcache_raw_read (regcache, >> gdbarch_tdep (gdbarch)->wb_regnum, buf); > > The "buf" can be removed by using regcache_raw_read_unsigned. > > -- > Yao (齐尧) Ok, the patch below makes that change. I want to make it clear that I do not have an xtensa machine. With the previous patch I was confident that it would not cause any regressions - as it only switched the define being used, and shouldn't cause any functional change. With the new patch there is more untested code and I am less confident that I've not introduced a subtle error. Tested on a --enable-targets=all build using make check with board files unix and native-gdbserver. Ok to commit (or the previous version? Alan. 2017-04-06 Alan Hayward * xtensa-tdep.c (XTENSA_MAX_REGISTER_SIZE): Add. (xtensa_register_write_masked): Use XTENSA_MAX_REGISTER_SIZE. (xtensa_register_read_masked): Likewise. (xtensa_pseudo_register_read): Use regcache_raw_read_unsigned. (xtensa_pseudo_register_write): Likewise. diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c index 13f1514e7651e47a268ef809b1324167f1f759bd..53c866075841fb00170cc34e446d6fc21c869032 100644 --- a/gdb/xtensa-tdep.c +++ b/gdb/xtensa-tdep.c @@ -120,6 +120,9 @@ static unsigned int xtensa_debug_level = 0; #define PS_WOE (1<<18) #define PS_EXC (1<<4) +/* Big enough to hold the size of the largest register in bytes. */ +#define XTENSA_MAX_REGISTER_SIZE 16 + static int windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) { @@ -370,7 +373,7 @@ static void xtensa_register_write_masked (struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0; /* Shift for next mask (mod 32). */ @@ -454,7 +457,7 @@ static enum register_status xtensa_register_read_masked (struct regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0; @@ -559,16 +562,15 @@ xtensa_pseudo_register_read (struct gdbarch *gdbarch, && (regnum >= gdbarch_tdep (gdbarch)->a0_base) && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) { - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); + ULONGEST value; enum register_status status; - status = regcache_raw_read (regcache, - gdbarch_tdep (gdbarch)->wb_regnum, - buf); + status = regcache_raw_read_unsigned (regcache, + gdbarch_tdep (gdbarch)->wb_regnum, + &value); if (status != REG_VALID) return status; - regnum = arreg_number (gdbarch, regnum, - extract_unsigned_integer (buf, 4, byte_order)); + regnum = arreg_number (gdbarch, regnum, value); } /* We can always read non-pseudo registers. */ @@ -656,12 +658,10 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch, && (regnum >= gdbarch_tdep (gdbarch)->a0_base) && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) { - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); - - regcache_raw_read (regcache, - gdbarch_tdep (gdbarch)->wb_regnum, buf); - regnum = arreg_number (gdbarch, regnum, - extract_unsigned_integer (buf, 4, byte_order)); + ULONGEST value; + regcache_raw_read_unsigned (regcache, + gdbarch_tdep (gdbarch)->wb_regnum, &value); + regnum = arreg_number (gdbarch, regnum, value); } /* We can always write 'core' registers.