Fwd: [PATCH, committed] i386: Clear vex instead of vex.evex
Commit Message
On Wed, Apr 4, 2018 at 8:33 AM, Joel Brobecker <brobecker@adacore.com> wrote:
>> > Looks good to me, but in that case, create a GDB PR that points
>> > to the binutils one, and set the Target Milestone to 8.1. This is
>> > to make sure all changes made on the 8.1 branch since the 8.1
>> > release are easily trackable by everyone.
>>
>> Done:
>> https://sourceware.org/bugzilla/show_bug.cgi?id=23028
>
> Perfect, thank you.
This is the patch I am checking in.
Thanks.
From f13be04ec6cc83947d8c4997aa48296a915b637f Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 4 Apr 2018 04:36:44 -0700
Subject: [PATCH] i386: Clear vex instead of vex.evex
"vex" has many fields to control how to decode an instruction. Clear
all fields in "vex" before decoding an instruction to avoid using values
left from the previous instruction.
gas/
PR gdb/23028
PR binutils/23025
* testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with
VEX and EVEX prefixes.
* testsuite/gas/i386/prefix.d: Updated.
opcodes/
PR gdb/23028
PR binutils/23025
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
to 0.
(print_insn): Clear vex instead of vex.evex.
(cherry picked from commit caf0678c84b5b55fbc4bcc853954745a4ad8b658)
---
gas/ChangeLog | 11 +++++++++++
gas/testsuite/gas/i386/prefix.d | 3 +++
gas/testsuite/gas/i386/prefix.s | 4 ++++
opcodes/ChangeLog | 11 +++++++++++
opcodes/i386-dis.c | 7 +------
5 files changed, 30 insertions(+), 6 deletions(-)
@@ -1,3 +1,14 @@
+2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backport from master branch
+ 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gdb/23028
+ PR binutils/23025
+ * testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with
+ VEX and EVEX prefixes.
+ * testsuite/gas/i386/prefix.d: Updated.
+
2018-01-04 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
@@ -72,5 +72,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: f2 0f c7 \(bad\)
[ ]*[a-f0-9]+: f0 90 lock nop
+[ ]*[a-f0-9]+: c5 fb e6 40 20 vcvtpd2dqx 0x20\(%eax\),%xmm0
+[ ]*[a-f0-9]+: 62 f1 ff 18 e6 40 04 vcvtpd2dq 0x20\(%eax\)\{1to2\},%xmm0
+[ ]*[a-f0-9]+: c5 fb e6 40 20 vcvtpd2dqx 0x20\(%eax\),%xmm0
...
#pass
@@ -391,5 +391,9 @@
nop
+ vcvtpd2dqx 0x20(%eax),%xmm0
+ vcvtpd2dq 0x20(%eax){1to2},%xmm0
+ vcvtpd2dqx 0x20(%eax),%xmm0
+
# Get a good alignment.
.p2align 4,0
@@ -1,3 +1,14 @@
+2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backport from master branch
+ 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gdb/23028
+ PR binutils/23025
+ * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
+ to 0.
+ (print_insn): Clear vex instead of vex.evex.
+
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
@@ -12815,7 +12815,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
@@ -12880,7 +12879,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
@@ -12918,12 +12916,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
/* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
VEX.vvvv is 1. */
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- vex.w = 0;
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
@@ -12998,7 +12994,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
@@ -13356,7 +13351,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
need_vex = 0;
need_vex_reg = 0;
vex_w_done = 0;
- vex.evex = 0;
+ memset (&vex, 0, sizeof (vex));
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
{
--
2.14.3