From patchwork Tue Dec 13 00:32:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18419 Received: (qmail 75906 invoked by alias); 13 Dec 2016 00:33:14 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 75871 invoked by uid 89); 13 Dec 2016 00:33:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=5218 X-HELO: mail-yw0-f180.google.com Received: from mail-yw0-f180.google.com (HELO mail-yw0-f180.google.com) (209.85.161.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Dec 2016 00:33:00 +0000 Received: by mail-yw0-f180.google.com with SMTP id a10so74858442ywa.3 for ; Mon, 12 Dec 2016 16:33:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=kWqhYgoTT5cmBM4Cn3ivhqa5Z8lUyVZkLaFV7TjDm9k=; b=WArmip+eOTODqkuSQDiMMs3c7iPNtuxT00XzCx+c3O1BbGtoz6jCXSp/SA4ieDtHr4 NHhjLrZA7vCHEYqHQgGD0rzUs26P+js90DP6moGcHipRVHdCYFNS4huU3r1lfvRfW5Ez BF69zIQ4+vcsaQe6VM2DAEq18J+CVJgr001cwO5g84loas15pse9bKYUAGrWsF71rBnb 3BPs+Q8pIr1m7owqgFn3Q6NZJ8YcRdBMaDm9rn4d+JJjYmnkMsZS/0vtZvzfFxaAWSbK aDIdlvfDkbffdFedll7xUdQ6G14kS06es1oc/nbejVjZeDbHnyzedCg3FOP8gOt/g54w ChdQ== X-Gm-Message-State: AKaTC03shpkTyxcq1tS3LezlG/kIcTD6dOWY7IToSiHmPZR8dXMsP2lBZgkwGlGfTz+jONFS/2YWoh0IVtBXcrMu X-Received: by 10.129.107.6 with SMTP id g6mr105769893ywc.78.1481589178742; Mon, 12 Dec 2016 16:32:58 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Mon, 12 Dec 2016 16:32:58 -0800 (PST) In-Reply-To: <20161212184245.GU10558@vapier.lan> References: <20161212184245.GU10558@vapier.lan> From: Jim Wilson Date: Mon, 12 Dec 2016 16:32:58 -0800 Message-ID: Subject: Re: [PATCH] fix for aarch64 sim tbnz bug To: Jim Wilson , "gdb-patches@sourceware.org" , Nick Clifton On Mon, Dec 12, 2016 at 10:42 AM, Mike Frysinger wrote: > i think you want to stuff those pass/fail strings into the > start macro instead of just having it get inserted where the > include happened to show up. That makes sense. Here is a new version of the patch with that change. Retested with a sim make check, and all tests pass. Jim 2016-12-12 Jim Wilson sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * fstur.s: New. * tbnz.s: New. diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/sim/aarch64/fstur.s new file mode 100644 index 0000000..2206ae5 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fstur.s @@ -0,0 +1,136 @@ +# mach: aarch64 + +# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq. +# Check the values -1, and XXX_MAX, which tests all bits. +# Check with offsets -256 and 255, which tests all bits. +# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq. + +.include "testutils.inc" + + .data +fm1: + .word 3212836864 +fmax: + .word 2139095039 +ftmp: + .word 0 + +dm1: + .word 0 + .word -1074790400 +dmax: + .word 4294967295 + .word 2146435071 +dtmp: + .word 0 + .word 0 + +ldm1: + .word 0 + .word 0 + .word 0 + .word -1073807360 +ldmax: + .word 4294967295 + .word 4294967295 + .word 4294967295 + .word 2147418111 +ldtmp: + .word 0 + .word 0 + .word 0 + .word 0 + + start + adrp x1, ftmp + add x1, x1, :lo12:ftmp + + adrp x0, fm1 + add x0, x0, :lo12:fm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur s2, [x5, #255] + stur s2, [x6, #255] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x0, fmax + add x0, x0, :lo12:fmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur s2, [x5, #-256] + stur s2, [x6, #-256] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x1, dtmp + add x1, x1, :lo12:dtmp + + adrp x0, dm1 + add x0, x0, :lo12:dm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur d2, [x5, #255] + stur d2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x0, dmax + add x0, x0, :lo12:dmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur d2, [x5, #-256] + stur d2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x1, ldtmp + add x1, x1, :lo12:ldtmp + + adrp x0, ldm1 + add x0, x0, :lo12:ldm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi v2.2d, #0 + ldur q2, [x5, #255] + stur q2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + adrp x0, ldmax + add x0, x0, :lo12:ldmax + add x5, x0, #256 + add x6, x1, #256 + movi v2.2d, #0 + ldur q2, [x5, #-256] + stur q2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/sim/aarch64/tbnz.s b/sim/testsuite/sim/aarch64/tbnz.s new file mode 100644 index 0000000..2416101 --- /dev/null +++ b/sim/testsuite/sim/aarch64/tbnz.s @@ -0,0 +1,55 @@ +# mach: aarch64 + +# Check the test-bit-and-branch instructions: tbnz, and tbz. +# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63. + +.include "testutils.inc" + + start + mov x0, #1 + tbnz x0, #0, .L1 + fail +.L1: + tbz x0, #0, .Lfailure + mov x0, #0xFFFFFFFFFFFFFFFE + tbnz x0, #0, .Lfailure + tbz x0, #0, .L2 + fail +.L2: + + mov x0, #0x80000000 + tbnz x0, #31, .L3 + fail +.L3: + tbz x0, #31, .Lfailure + mov x0, #0xFFFFFFFF7FFFFFFF + tbnz x0, #31, .Lfailure + tbz x0, #31, .L4 + fail +.L4: + + mov x0, #0x100000000 + tbnz x0, #32, .L5 + fail +.L5: + tbz x0, #32, .Lfailure + mov x0, #0xFFFFFFFEFFFFFFFF + tbnz x0, #32, .Lfailure + tbz x0, #32, .L6 + fail +.L6: + + mov x0, #0x8000000000000000 + tbnz x0, #63, .L7 + fail +.L7: + tbz x0, #63, .Lfailure + mov x0, #0x7FFFFFFFFFFFFFFF + tbnz x0, #63, .Lfailure + tbz x0, #63, .L8 + fail +.L8: + + pass +.Lfailure: + fail diff --git a/sim/testsuite/sim/aarch64/testutils.inc b/sim/testsuite/sim/aarch64/testutils.inc index c8897aa..1fc9bc8 100644 --- a/sim/testsuite/sim/aarch64/testutils.inc +++ b/sim/testsuite/sim/aarch64/testutils.inc @@ -43,10 +43,6 @@ swiwrite 5 exit 0 - - .data -.Lpass: - .asciz "pass\n" .endm # MACRO: fail @@ -56,16 +52,18 @@ adrp x1, .Lfail add x1, x1, :lo12:.Lfail swiwrite 5 - exit 0 - - .data -.Lfail: - .asciz "fail\n" + exit 1 .endm # MACRO: start # All assembler tests should start with a call to "start" .macro start + .data +.Lpass: + .asciz "pass\n" +.Lfail: + .asciz "fail\n" + .text .global _start _start: