From patchwork Tue Dec 27 02:34:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18692 Received: (qmail 47587 invoked by alias); 27 Dec 2016 02:35:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 47391 invoked by uid 89); 27 Dec 2016 02:34:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=signbit X-HELO: mail-yw0-f177.google.com Received: from mail-yw0-f177.google.com (HELO mail-yw0-f177.google.com) (209.85.161.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Dec 2016 02:34:48 +0000 Received: by mail-yw0-f177.google.com with SMTP id r204so162155959ywb.0 for ; Mon, 26 Dec 2016 18:34:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=ANOU54M2JVDf0At1PrCcX+EaV/MsUcg+nRu0MIWsFvw=; b=WGYtLABRDGAGfkUBHb3btaEUiGwY0peo/7vcpUFhagBy+02KRDZQx3ZnU5GtOKYOQq oFEUgtzlpcSq5eRCwhvMsT29VClqmsQfvba5mrO/KljCSOhMT2Xl4ml8bQrzm2xdtarU /2kIh5IDKE0Pu1417XfqYeAubquUI0uxPLwsascHrEklSOPaPXqFfAaP4NYlplnYxk7x DT1fg3OME9yA0T6P92kgN+Q5KsGvwOOpvLJ9U9UcjA9noJhLmak+UgdW15Uwt7WGJzgY PKXWMekIYDT20jDSR9BqIb1lrpODrfMcDswhelpbrVGiBMJQjPwR1Cbj7M6hm9ShEfBQ Fiig== X-Gm-Message-State: AIkVDXK8FyQ/uoSg6Rgdo2T1mXZr5evi95yYiuq9K3uAV5Nwdu6CqC0GaQeR5ezF3r/6qfkM/QwbHpjRw+2xh9Jb X-Received: by 10.129.163.69 with SMTP id a66mr24701750ywh.175.1482806086592; Mon, 26 Dec 2016 18:34:46 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Mon, 26 Dec 2016 18:34:46 -0800 (PST) From: Jim Wilson Date: Mon, 26 Dec 2016 18:34:46 -0800 Message-ID: Subject: [PATCH] aarch64 sim fcsel bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The fcsel instruction is storing source register numbers in the destination register, instead of source register contents. There are missing calls to fetch the contents of the source registers. While looking at this, I ran into the problem that when an FP register changes from plus zero to minus zero, or vice versa, I don't get any output with --trace-register. The GCC C testcase I was looking at happened to be testing support for signed zeros, and the source register number happened to be zero, so I needed this to work right to see what was going wrong. I added signbit calls to catch this case. The testcase fails without the patch, and works with the patch. The GCC C testsuite unexpected failures drop from 2473 to 2416. Jim sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. sim/testsuite/sim/aarch64/ * fcsel.s: New. diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c index 648221f..4b201a7 100644 --- a/sim/aarch64/cpustate.c +++ b/sim/aarch64/cpustate.c @@ -20,6 +20,7 @@ along with this program. If not, see . */ #include +#include #include "sim-main.h" #include "cpustate.h" @@ -369,7 +370,9 @@ aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val) void aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) { - if (val != cpu->fr[reg].s) + if (val != cpu->fr[reg].s + /* Handle +/- zero. */ + || signbit (val) != signbit (cpu->fr[reg].s)) { FRegister v; @@ -385,7 +388,9 @@ aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) void aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) { - if (val != cpu->fr[reg].d) + if (val != cpu->fr[reg].d + /* Handle +/- zero. */ + || signbit (val) != signbit (cpu->fr[reg].d)) { FRegister v; diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index be3d6c7..3f56177 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -7463,9 +7463,11 @@ dexSimpleFPCondSelect (sim_cpu *cpu) TRACE_DECODE (cpu, "emulated at line %d", __LINE__); if (INSTR (22, 22)) - aarch64_set_FP_double (cpu, sd, set ? sn : sm); + aarch64_set_FP_double (cpu, sd, (set ? aarch64_get_FP_double (cpu, sn) + : aarch64_get_FP_double (cpu, sm))); else - aarch64_set_FP_float (cpu, sd, set ? sn : sm); + aarch64_set_FP_float (cpu, sd, (set ? aarch64_get_FP_float (cpu, sn) + : aarch64_get_FP_float (cpu, sm))); } /* Store 32 bit unscaled signed 9 bit. */ diff --git a/sim/testsuite/sim/aarch64/fcsel.s b/sim/testsuite/sim/aarch64/fcsel.s new file mode 100644 index 0000000..5b8443c --- /dev/null +++ b/sim/testsuite/sim/aarch64/fcsel.s @@ -0,0 +1,53 @@ +# mach: aarch64 + +# Check the FP Conditional Select instruction: fcsel. +# Check 1/1 eq/neg, and 1/2 lt/gt. + +.include "testutils.inc" + + start + fmov s0, #1.0 + fmov s1, #1.0 + fmov s2, #-1.0 + fcmp s0, s1 + fcsel s3, s0, s2, eq + fcmp s3, s0 + bne .Lfailure + fcsel s3, s0, s2, ne + fcmp s3, s2 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #2.0 + fcmp s0, s1 + fcsel s3, s0, s2, lt + fcmp s3, s0 + bne .Lfailure + fcsel s3, s0, s2, gt + fcmp s3, s2 + bne .Lfailure + + fmov d0, #1.0 + fmov d1, #1.0 + fmov d2, #-1.0 + fcmp d0, d1 + fcsel d3, d0, d2, eq + fcmp d3, d0 + bne .Lfailure + fcsel d3, d0, d2, ne + fcmp d3, d2 + bne .Lfailure + + fmov d0, #1.0 + fmov d1, #2.0 + fcmp d0, d1 + fcsel d3, d0, d2, lt + fcmp d3, d0 + bne .Lfailure + fcsel d3, d0, d2, gt + fcmp d3, d2 + bne .Lfailure + + pass +.Lfailure: + fail