From patchwork Sun Mar 26 03:40:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 19730 Received: (qmail 38387 invoked by alias); 26 Mar 2017 03:40:15 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38305 invoked by uid 89); 26 Mar 2017 03:40:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*Ad:U*gdb-patches, Hx-languages-length:2118, 1445 X-HELO: mail-lf0-f53.google.com Received: from mail-lf0-f53.google.com (HELO mail-lf0-f53.google.com) (209.85.215.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 26 Mar 2017 03:40:11 +0000 Received: by mail-lf0-f53.google.com with SMTP id x137so8089904lff.3 for ; Sat, 25 Mar 2017 20:40:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=c+pcPXLBSfYzR8yZszDcqacmUIO6nDAmhxzCELni6aU=; b=j9KhU+6X/BcAfy2k1cTEKLAJe/A+dznzLLKeCyN45HRTxR8IBbsGFrEMr2IMlXKYc0 zwk/rE5J2mfwEmwunyXznmF6E16aOhfgNsYIMzKA03Kh0AVJXwBKgd05BHuhLQw20P/H ZD1o3eKd2PBcwiGZgo5Zvcxak+fegHOyR+rAkEXLqVWeakvGg5W9kTB4uRwp5TUXSaZM PCESarRo1ohmoZaJPwVgwZSCrHvDyZ6Mz7UIKLeRqy7zHHyhZgF0m+xLmPNlkoGHf317 KDZPRHSGt3FWMFCCGQwoiPSuvi8cOgTjY7Hfgxpw3d3iYiFtGDwRrlqvFEXidwyNoc7t xOtQ== X-Gm-Message-State: AFeK/H2WRk6lkiAvWpPDP7kE+eqSM/iQqw+K5qCI/mAOi+HOW+6t2isoLTfdZ7mw7hbNTG+vhZiFddRvtTfm49/w X-Received: by 10.25.181.194 with SMTP id g63mr6816667lfk.47.1490499610311; Sat, 25 Mar 2017 20:40:10 -0700 (PDT) MIME-Version: 1.0 Received: by 10.25.162.145 with HTTP; Sat, 25 Mar 2017 20:40:09 -0700 (PDT) From: Jim Wilson Date: Sat, 25 Mar 2017 20:40:09 -0700 Message-ID: Subject: [PATCH] aarch64 sim adds C flag bug fix To: gdb-patches@sourceware.org This fixes a problem where the C flag was incorrectly set when adding a large negative value with a small positive value. The word signed result needs to be cast to unsigned to avoid a sign extension before comparing with the double word unsigned result. The modified testcase fails without the patch and works with the patch. This patch reduces GCC C testsuite unexpected failures from 1445 to 1439 (-6). Jim 2017-03-25 Jim Wilson sim/aarch64/ * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry flag check. sim/testsuite/sim/aarch64/ * adds.s: Add checks for values -2 and 1, where C is not set. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 8a8df7a..f0668ad 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -1650,7 +1650,7 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2) if (result & (1 << 31)) flags |= N; - if (uresult != result) + if (uresult != (uint32_t)result) flags |= C; if (sresult != result) diff --git a/sim/testsuite/sim/aarch64/adds.s b/sim/testsuite/sim/aarch64/adds.s index 2bc240c..fdea5a7 100644 --- a/sim/testsuite/sim/aarch64/adds.s +++ b/sim/testsuite/sim/aarch64/adds.s @@ -3,6 +3,7 @@ # Check the basic integer compare instructions: adds, adds64, subs, subs64. # For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C), # and MIN_INT and -1 (V), +# Also check -2 and 1 (not C). # For sub, negate the second value. .include "testutils.inc" @@ -24,6 +25,10 @@ mov w1, #-1 adds w2, w0, w1 bvc .Lfailure + mov w0, #-2 + mov w1, #1 + adds w2, w0, w1 + bcs .Lfailure mov x0, #1 mov x1, #-1 @@ -41,6 +46,10 @@ mov x1, #-1 adds x2, x0, x1 bvc .Lfailure + mov x0, #-2 + mov x1, #1 + adds x2, x0, x1 + bcs .Lfailure mov w0, #1 mov w1, #1 @@ -58,6 +67,10 @@ mov w1, #1 subs w2, w0, w1 bvc .Lfailure + mov w0, #-2 + mov w1, #-1 + subs w2, w0, w1 + bcs .Lfailure mov x0, #1 mov x1, #1 @@ -75,6 +88,10 @@ mov x1, #1 subs x2, x0, x1 bvc .Lfailure + mov x0, #-2 + mov x1, #-1 + subs x2, x0, x1 + bcs .Lfailure pass .Lfailure: