From patchwork Sun Feb 26 03:53:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 19386 Received: (qmail 63545 invoked by alias); 26 Feb 2017 03:54:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 63371 invoked by uid 89); 26 Feb 2017 03:53:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Wilson, sim X-HELO: mail-wr0-f181.google.com Received: from mail-wr0-f181.google.com (HELO mail-wr0-f181.google.com) (209.85.128.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 26 Feb 2017 03:53:47 +0000 Received: by mail-wr0-f181.google.com with SMTP id g10so32826250wrg.2 for ; Sat, 25 Feb 2017 19:53:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=/2Av0JlKPM/rx8xGhXyZCbUDXE9fANwWb+Q0z6cn8Bc=; b=ZcPvMx7N1cHmOigrlXwc0W6vXkqjnV3cg6QtxdPL27pbGvQoZxXf/i7dKUmsjLowPz mIIgk0qbONCj1ZxDGupq34xM2a9YsQeyat6zKeeHXbebwt+sn/t/8cmuAyyylZpu2gwO orC/n8a6lXRuB1BkNJttxuXa660miBPclW4o4JfwhpUCJdWH4Pi1/WGDyEZ7k2WqmjdX E0qOaBXQxg1k/fJdCsfruePmDRPx6YqtOCk42b2n7f+oTnZgACACUJ4J6HTrQ+vPq93V SfdFf49vi5Bb1Vhmf4uvNXfzMmONo/2CG9y6gV5tc9qOZ3eT5k6iyJkj99HxF0yrCSYd +kfA== X-Gm-Message-State: AMke39klpCpf0qstNncNpBwuitNimFC7JnDXwzGHH8Wdy+TX7W7c7NLjNjO71lD83vhk/GSEPSMemL9EG8tsEevT X-Received: by 10.223.165.138 with SMTP id g10mr9353162wrc.105.1488081225100; Sat, 25 Feb 2017 19:53:45 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.145.68 with HTTP; Sat, 25 Feb 2017 19:53:44 -0800 (PST) From: Jim Wilson Date: Sat, 25 Feb 2017 19:53:44 -0800 Message-ID: Subject: [PATCH] aarch64 sim, add cnt insn support To: gdb-patches@sourceware.org This patch adds missing support for the cnt (popcount) instruction. The new testcase fails without the patch and works with the patch. This patch reduces GCC C testsuite failures from 1510 to 1493 (-17). Jim 2017-02-25 Jim Wilson sim/aarch64/ * simulator.c (popcount): New. (do_vec_CNT): New. (do_vec_op1): Add do_vec_CNT call. sim/testsuite/sim/aarch64/ * cnt.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index d31cb10..f66ca78 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -4197,6 +4288,56 @@ do_vec_XTN (sim_cpu *cpu) } } +/* Return the number of bits set in the input value. */ +#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) +# define popcount __builtin_popcount +#else +static int +popcount (unsigned char x) +{ + static const unsigned char popcnt[16] = + { + 0, 1, 1, 2, + 1, 2, 2, 3, + 1, 2, 2, 3, + 2, 3, 3, 4 + }; + + /* Only counts the low 8 bits of the input as that is all we need. */ + return popcnt[x % 16] + popcnt[x / 16]; +} +#endif + +static void +do_vec_CNT (sim_cpu *cpu) +{ + /* instr[31] = 0 + instr[30] = half (0)/ full (1) + instr[29,24] = 00 1110 + instr[23,22] = size: byte(00) + instr[21,10] = 1000 0001 0110 + instr[9,5] = Vs + instr[4,0] = Vd. */ + + unsigned vs = INSTR (9, 5); + unsigned vd = INSTR (4, 0); + int full = INSTR (30, 30); + int size = INSTR (23, 22); + int i; + + NYI_assert (29, 24, 0x0E); + NYI_assert (21, 10, 0x816); + + if (size != 0) + HALT_UNALLOC; + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + + for (i = 0; i < (full ? 16 : 8); i++) + aarch64_set_vec_u8 (cpu, vd, i, + popcount (aarch64_get_vec_u8 (cpu, vs, i))); +} + static void do_vec_maxv (sim_cpu *cpu) { @@ -5605,6 +5691,7 @@ do_vec_op1 (sim_cpu *cpu) case 0x08: do_vec_sub_long (cpu); return; case 0x0a: do_vec_XTN (cpu); return; case 0x11: do_vec_SSHL (cpu); return; + case 0x16: do_vec_CNT (cpu); return; case 0x19: do_vec_max (cpu); return; case 0x1B: do_vec_min (cpu); return; case 0x21: do_vec_add (cpu); return; diff --git a/sim/testsuite/sim/aarch64/cnt.s b/sim/testsuite/sim/aarch64/cnt.s new file mode 100644 index 0000000..cf53fe0 --- /dev/null +++ b/sim/testsuite/sim/aarch64/cnt.s @@ -0,0 +1,33 @@ +# mach: aarch64 + +# Check the popcount instruction: cnt. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x0f070605 + .word 0x44332211 + .word 0xff776655 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + cnt v1.8b, v0.8b + addv b2, v1.8b + mov x1, v2.d[0] + cmp x1, #16 + bne .Lfailure + + cnt v1.16b, v0.16b + addv b2, v1.16b + mov x1, v2.d[0] + cmp x1, #48 + bne .Lfailure + + pass +.Lfailure: + fail