From patchwork Fri Mar 3 21:25:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 19429 Received: (qmail 92063 invoked by alias); 3 Mar 2017 21:25:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 92005 invoked by uid 89); 3 Mar 2017 21:25:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=1473, 509, products X-HELO: mail-wr0-f182.google.com Received: from mail-wr0-f182.google.com (HELO mail-wr0-f182.google.com) (209.85.128.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Mar 2017 21:25:02 +0000 Received: by mail-wr0-f182.google.com with SMTP id l37so81876915wrc.1 for ; Fri, 03 Mar 2017 13:25:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=to0cw7C6pyP2T/8p2NhNbjmV7F+hPYKoG/INnJ+OS7U=; b=bHTDKTEkGyvfLWet1eeyI0TQmtgG1t7hSIBmhgDvZ1txh9bn08HISR0QsvonM5Q0F6 UwxxsY5pHIS5LnCoyWSVvmG0Yq9gUSdlyaT52mhNCco6P7GeA4ZgvWfa2vZ8k4RNh5TJ zG4PWQrXYPD9r+wtledbDo6uod4Jip/uY/+o2iOaRsEqlUAxN/cO5l+5+fui/reD6f4o wh2XNNI2AoW2JELY0SYeUR1ELozIbna2KdtBnD86zL6yh2XuLsMLULQavdtfegzCs1UT nmhW1HqNSf6oPNUCbf92MDm1WaE7FT0HJCTAOeuC4iquRi78MuSC5hJPtuT/q6kri2M0 KB2A== X-Gm-Message-State: AMke39kmr/XqIcTwtDflPiOWK2qzYx0ePep4yCec4RRw04T2uvhmTc/XhxS2ug5uqAU59b1s681zvetoukbUuz4G X-Received: by 10.223.135.237 with SMTP id c42mr4316961wrc.139.1488576301133; Fri, 03 Mar 2017 13:25:01 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.145.68 with HTTP; Fri, 3 Mar 2017 13:25:00 -0800 (PST) From: Jim Wilson Date: Fri, 3 Mar 2017 13:25:00 -0800 Message-ID: Subject: [PATCH] aarch64 sim umulh/smulh fixes To: gdb-patches@sourceware.org Umulh gets the wrong result when the middle cross products generate a carry out, as it is being added in the wrong place. This is fixed by shifting it left by 32. Smulh gets the wrong result if the low part multiply isn't zero. In this case, we want to invert instead of negating. It also fails if the high part ends up 0 and the low part isn't, since multiply by -1 doesn't do anything in that case. Fixed by using the ~ operator instead, and then adding in carry if the low part is 0. The new testcase works with the patch, and fails without. The patch reduces gcc C testsuite unexpected failures from 1473 to 1440 (-33). This also fixes bugs in last weeks sumov.s testcase. Somehow I accidentally committed the unfinished version of it. The corrected version after this patch works. Jim 2017-03-03 Jim Wilson sim/aarch64/ * simulator.c (mul64hi): Shift carry left by 32. (smulh): Change signum to negate. If negate, invert result, and add carry bit if low part of multiply result is zero. sim/testsuite/sim/aarch64/ * sumov.s: Correct compare test values. * sumulh.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 1756ba1..8a8df7a 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -13020,6 +13020,8 @@ mul64hi (uint64_t value1, uint64_t value2) /* Drop lowest 32 bits of middle cross-product. */ result = resultmid1 >> 32; + /* Move carry bit to just above middle cross-product highest bit. */ + carry = carry << 32; /* Add top cross-product plus and any carry. */ result += xproducthi + carry; @@ -13042,7 +13044,7 @@ smulh (sim_cpu *cpu) int64_t value2 = aarch64_get_reg_u64 (cpu, rm, NO_SP); uint64_t uvalue1; uint64_t uvalue2; - int64_t signum = 1; + int negate = 0; if (ra != R31) HALT_UNALLOC; @@ -13051,7 +13053,7 @@ smulh (sim_cpu *cpu) the fix the sign up afterwards. */ if (value1 < 0) { - signum *= -1L; + negate = !negate; uvalue1 = -value1; } else @@ -13061,7 +13063,7 @@ smulh (sim_cpu *cpu) if (value2 < 0) { - signum *= -1L; + negate = !negate; uvalue2 = -value2; } else @@ -13070,9 +13072,18 @@ smulh (sim_cpu *cpu) } TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + uresult = mul64hi (uvalue1, uvalue2); result = uresult; - result *= signum; + + if (negate) + { + /* Multiply 128-bit result by -1, which means highpart gets inverted, + and has carry in added only if low part is 0. */ + result = ~result; + if ((uvalue1 * uvalue2) == 0) + result += 1; + } aarch64_set_reg_s64 (cpu, rd, NO_SP, result); } diff --git a/sim/testsuite/sim/aarch64/sumov.s b/sim/testsuite/sim/aarch64/sumov.s index 69021cb..7180c6a 100644 --- a/sim/testsuite/sim/aarch64/sumov.s +++ b/sim/testsuite/sim/aarch64/sumov.s @@ -34,7 +34,7 @@ input: smov w1, v0.h[4] cmp w0, #0x0201 bne .Lfailure - cmp w1, #-2315 + cmp w1, #-3343 bne .Lfailure smov x0, v0.h[1] @@ -50,8 +50,9 @@ input: movk x2, #0x0807, lsl #16 cmp x0, x2 bne .Lfailure - mov x3, #0xf6f5 - movk x3, #0xf8f7, lsl #16 + mov w3, #0xf6f5 + movk w3, #0xf8f7, lsl #16 + sxtw x3, w3 cmp x1, x3 bne .Lfailure @@ -64,9 +65,10 @@ input: umov w0, v0.h[0] umov w1, v0.h[4] - cmp w0, #0201 + cmp w0, #0x0201 bne .Lfailure - cmp w1, #0xf2f1 + mov w2, #0xf2f1 + cmp w1, w2 bne .Lfailure umov w0, v0.s[0] diff --git a/sim/testsuite/sim/aarch64/sumulh.s b/sim/testsuite/sim/aarch64/sumulh.s new file mode 100644 index 0000000..17f1ecd --- /dev/null +++ b/sim/testsuite/sim/aarch64/sumulh.s @@ -0,0 +1,56 @@ +# mach: aarch64 + +# Check the multiply highpart instructions: smulh, umulh. + +# Test -2*2, -1<<32*-1<<32, -2*-2, and 2*2. + +.include "testutils.inc" + + .data + .align 4 + + start + + mov x0, #-2 + mov x1, #2 + smulh x2, x0, x1 + cmp x2, #-1 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #1 + bne .Lfailure + + mov w0, #-1 + lsl x0, x0, #32 // 0xffffffff00000000 + mov x1, x0 + smulh x2, x0, x1 + cmp x2, #1 + bne .Lfailure + umulh x3, x0, x1 + mov w4, #-2 + lsl x4, x4, #32 + add x4, x4, #1 // 0xfffffffe00000001 + cmp x3, x4 + bne .Lfailure + + mov x0, #-2 + mov x1, #-2 + smulh x2, x0, x1 + cmp x2, #0 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #-4 + bne .Lfailure + + mov x0, #2 + mov x1, #2 + smulh x2, x0, x1 + cmp x2, #0 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #0 + bne .Lfailure + + pass +.Lfailure: + fail