From patchwork Sun Jan 22 21:57:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18987 Received: (qmail 102726 invoked by alias); 22 Jan 2017 21:57:39 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 102700 invoked by uid 89); 22 Jan 2017 21:57:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_SORBS_SPAM, SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=ham version=3.3.2 spammy=1104, 2108, 0x00000002, sim_cpu X-HELO: mail-yb0-f177.google.com Received: from mail-yb0-f177.google.com (HELO mail-yb0-f177.google.com) (209.85.213.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 22 Jan 2017 21:57:28 +0000 Received: by mail-yb0-f177.google.com with SMTP id l23so82271958ybj.2 for ; Sun, 22 Jan 2017 13:57:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=oA8PNwXpFZ0GROHMARsKfFbp7WwX8sD+UIbiK3DW84w=; b=bSr9/tdWMWl7xY/eEBsjM/jnrmy5hIPaOz+NAr4x6NhnuJRaYZrha5e5L5fyDh2plp 1A7begyL0uH02xsuJKZiw+hAWldWWumcuEj0xGiA75Bpq0BsJwr30Lm1WPLdCAuD3arc Tj6mzrUM/1SEBbYmYXl90C8COneu5IbjEghdBFC159BCWAkHKj/pO3gQYY09wg6ob5Ir JkicoeZwtUG8XTfVfwkMXv9YymLWLcs59lt8Q3cuzX9votghtt6kOxUCYcJ0Qvamw1Ab B47ZkxGfSmMPvrf5A5igrd6AU6x4+uY3Q7HAlpMFiAOlqY1apWGwDVgrBsKCM0WcDZTq L9Kg== X-Gm-Message-State: AIkVDXK5ahfuSu0eW3TPPwgLU14w2N2V32DtBYumeOuI038439h1miDtWmgEoit39OhfRm2K0YvTEd2qp+vm+SvX X-Received: by 10.37.192.199 with SMTP id c190mr2032272ybf.28.1485122246848; Sun, 22 Jan 2017 13:57:26 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.37.1 with HTTP; Sun, 22 Jan 2017 13:57:26 -0800 (PST) From: Jim Wilson Date: Sun, 22 Jan 2017 13:57:26 -0800 Message-ID: Subject: [PATCH] aarch64 sim cmtst bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The cmtst instruction isn't recognized. Just adding one line fixes it. The testcase fails without the patch and works with the patch. The patch reduces GCC C testsuite failures from 2108 to 2096 (-12). Jim sim/aarch64/ * simulator.c (do_vec_compare): Add case 0x23 for CMTST. sim/testsuite/sim/aarch64/ * cmtst.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index c8e65c5..a44e70a 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -4742,6 +4742,7 @@ do_vec_compare (sim_cpu *cpu) case 0x0D: /* 0001101 GT */ VEC_CMP (s, > ); case 0x0F: /* 0001111 GE */ VEC_CMP (s, >= ); case 0x22: /* 0100010 GT #0 */ VEC_CMP0 (s, > ); + case 0x23: /* 0100011 TST */ VEC_CMP (u, & ); case 0x26: /* 0100110 EQ #0 */ VEC_CMP0 (s, == ); case 0x2A: /* 0101010 LT #0 */ VEC_CMP0 (s, < ); case 0x4D: /* 1001101 HI */ VEC_CMP (u, > ); diff --git a/sim/testsuite/sim/aarch64/cmtst.s b/sim/testsuite/sim/aarch64/cmtst.s new file mode 100644 index 0000000..64c8b27 --- /dev/null +++ b/sim/testsuite/sim/aarch64/cmtst.s @@ -0,0 +1,104 @@ +# mach: aarch64 + +# Check the vector compare bitwise test instruction: cmtst. + +.include "testutils.inc" + + .data + .align 4 +inputb: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +inputh: + .word 0x00020001 + .word 0x00040003 + .word 0x00060005 + .word 0x00800007 +inputs: + .word 0x00000001 + .word 0x00000002 + .word 0x00000003 + .word 0x00000004 +inputd: + .word 0x00000001 + .word 0x00000000 + .word 0x00000002 + .word 0x00000000 +inputd2: + .word 0x00000003 + .word 0x00000000 + .word 0x00000004 + .word 0x00000000 + + start + adrp x0, inputb + ldr q0, [x0, #:lo12:inputb] + rev64 v1.16b, v0.16b + + cmtst v2.8b, v0.8b, v1.8b + addv b3, v2.8b + mov x1, v3.d[0] + cmp x1, #0x5fa + bne .Lfailure + + cmtst v2.16b, v0.16b, v1.16b + addv b3, v2.16b + mov x1, v3.d[0] + cmp x1, #0xbf4 + bne .Lfailure + + adrp x0, inputh + ldr q0, [x0, #:lo12:inputh] + rev64 v1.8h, v0.8h + + cmtst v2.4h, v0.4h, v1.4h + addv h3, v2.4h + mov x1, v3.d[0] + mov x2, #0x1fffe + cmp x1, x2 + bne .Lfailure + + cmtst v2.8h, v0.8h, v1.8h + addv h3, v2.8h + mov x1, v3.d[0] + mov x2, #0x3fffc + cmp x1, x2 + bne .Lfailure + + adrp x0, inputs + ldr q0, [x0, #:lo12:inputs] + mov v1.d[0], v0.d[1] + mov v1.d[1], v0.d[0] + rev64 v1.4s, v1.4s + + cmtst v2.2s, v0.2s, v1.2s + mov x1, v2.d[0] + mov x2, #0xffffffff00000000 + cmp x1, x2 + bne .Lfailure + + cmtst v2.4s, v0.4s, v1.4s + addv s3, v2.4s + mov x1, v3.d[0] + mov x2, #0x1fffffffe + cmp x1, x2 + bne .Lfailure + + adrp x0, inputd + ldr q0, [x0, #:lo12:inputd] + adrp x0, inputd2 + ldr q1, [x0, #:lo12:inputd2] + + cmtst v2.2d, v0.2d, v1.2d + mov x1, v2.d[0] + cmp x1, #-1 + bne .Lfailure + mov x2, v2.d[1] + cmp x2, #0 + bne .Lfailure + + pass +.Lfailure: + fail