From patchwork Fri Jun 3 02:36:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 12729 Received: (qmail 43745 invoked by alias); 3 Jun 2016 02:36:43 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 43729 invoked by uid 89); 3 Jun 2016 02:36:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=littleendian, shortly, team X-HELO: mail-oi0-f48.google.com Received: from mail-oi0-f48.google.com (HELO mail-oi0-f48.google.com) (209.85.218.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 03 Jun 2016 02:36:32 +0000 Received: by mail-oi0-f48.google.com with SMTP id k23so107171707oih.0 for ; Thu, 02 Jun 2016 19:36:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to; bh=8/Z89oJ0L/e5rzJCshmw+ILSfE3IiZ8JtKsF//wAtDg=; b=AbNL7WkovvnfjnAMu8Mfe0/c2EjrLAjy+mnutkRj9QhXr/5Qs3EXAa3+I1AnSTkned Si8e7mFO2kMbFPcc8N7bk3kIJqnieo5aDU5n7kDP5vxMHnki9IQbk9tSz4rhhGnrAffa gNI+ZVCaHny50p9Cpl9KtzYoIahTtAT0AcWdSJObTDf/BRMXjRettM9gsmWdr7bg+OmG kMLMzS/ddqwJQaBNqm6Zg3VRuqFAvILdWilc1mpmtj1yNSiYcF8B9b5EcksjRuAvewrm DAu0w1hBTT9+oWfJ53p0nBLeWINw97zep6hdwQuA18rh/neKQ746RSgSa/1tcKnDE5l0 oCJw== X-Gm-Message-State: ALyK8tIpgAXaf2TStkXDxKTTugQCi7mVleYvbqN4w1b3qYSMdwxU8Kp6VOMJ8ckVo3a/doUOU/lz9P2FUx2UAsKc MIME-Version: 1.0 X-Received: by 10.202.85.145 with SMTP id j139mr588487oib.100.1464921390313; Thu, 02 Jun 2016 19:36:30 -0700 (PDT) Received: by 10.157.35.91 with HTTP; Thu, 2 Jun 2016 19:36:30 -0700 (PDT) Date: Thu, 2 Jun 2016 19:36:30 -0700 Message-ID: Subject: [PATCH] aarch64 sim big-endian support From: Jim Wilson To: gdb-patches@sourceware.org On aarch64, code is always little-endian, even when compiling big-endian, so we need to force little-endian when reading instructions. Running the gcc C language testsuite, I get for an aarch64-elf target # of expected passes 35433 # of unexpected failures 254 # of unsupported tests 131 and for an aarch64_be-elf target with the attached patch I get # of expected passes 35200 # of unexpected failures 487 # of unsupported tests 131 so this simple patch gets us most of the way there. I haven't tried looking at the other problems yet. I also have a dejagnu patch I wrote to make this work, which I will be submitting to the dejagnu team shortly. Jim 2016-06-02 Jim Wilson sim/aarch64/ * simulator.c (aarch64_step): New var saved_target_byte_order. Force byte order to BFD_ENDIAN_LITTLE before pc read, then restore saved value. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 88cb03d..5a1814c 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -14078,12 +14078,18 @@ static bfd_boolean aarch64_step (sim_cpu *cpu) { uint64_t pc = aarch64_get_PC (cpu); + enum bfd_endian saved_target_byte_order; if (pc == TOP_LEVEL_RETURN_PC) return FALSE; aarch64_set_next_PC (cpu, pc + 4); + + /* Code is always little-endian. */ + saved_target_byte_order = current_target_byte_order; + current_target_byte_order = BFD_ENDIAN_LITTLE; aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc); + current_target_byte_order = saved_target_byte_order; TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc, aarch64_get_instr (cpu));