From patchwork Fri May 5 08:03:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 20290 Received: (qmail 59563 invoked by alias); 5 May 2017 08:03:42 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 59540 invoked by uid 89); 5 May 2017 08:03:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0059.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.59) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 05 May 2017 08:03:39 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com (10.160.211.19) by AM3PR08MB0104.eurprd08.prod.outlook.com (10.160.211.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1061.12; Fri, 5 May 2017 08:03:36 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::b823:64c1:afc5:3a08]) by AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::b823:64c1:afc5:3a08%17]) with mapi id 15.01.1061.022; Fri, 5 May 2017 08:03:36 +0000 From: Alan Hayward To: Yao Qi CC: "gdb-patches@sourceware.org" , nd Subject: Re: [PATCH 3/11] Add MIPS_MAX_REGISTER_SIZE (1/4) Date: Fri, 5 May 2017 08:03:36 +0000 Message-ID: References: <3C00280E-37C9-4C0A-9DA6-F3B9DB1A6E8F@arm.com> <86y3v7uf9j.fsf@gmail.com> In-Reply-To: <86y3v7uf9j.fsf@gmail.com> authentication-results: gmail.com; dkim=none (message not signed) header.d=none; gmail.com; dmarc=none action=none header.from=arm.com; x-microsoft-exchange-diagnostics: 1; AM3PR08MB0104; 7:Cd4btr9mC2u7z8Ev+s4zIEhbvU/cU8ZHnzH7GaHV6LKjEx59PYsHIgEbWIkFL51cNecw3aNqZhTV/nWAdMI0sJIAT1ZbriTQv+agrK3Jhi7kpeEZg6BDEy4S4nGkz2B+nH0dtHNbaSB/Yn/KlRQ8KzvG0KQzgIm9b5E99E9cgQRduBV6f15teo9ClN7jLTIffPnkNBjW3bGuY+L+B1Gx2q7fy3wGlCTR0zT9P93Oy0yoCm2vYAgMc1UpaJXVQwIZ6TyIqu1dtsQ//H2avqb2Jq4yW7Culz9m2amX+Tc1KJ3xFdcq6upos1yZv+h/QaK05eXIfwxmAgc26joAEelBeQ== x-ms-office365-filtering-correlation-id: 50459574-e119-45af-46ad-08d4938d3bd5 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075); SRVR:AM3PR08MB0104; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93001095)(6055026)(6041248)(20161123555025)(20161123562025)(20161123560025)(20161123564025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148); SRVR:AM3PR08MB0104; BCL:0; PCL:0; RULEID:; SRVR:AM3PR08MB0104; x-forefront-prvs: 02981BE340 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39410400002)(39450400003)(39860400002)(39400400002)(39840400002)(39850400002)(377424004)(24454002)(39060400002)(53546009)(6116002)(3846002)(5250100002)(102836003)(33656002)(4326008)(83716003)(6246003)(38730400002)(110136004)(53936002)(6512007)(54356999)(76176999)(6436002)(6486002)(6506006)(229853002)(2950100002)(6916009)(25786009)(5660300001)(86362001)(7736002)(2906002)(1411001)(3660700001)(3280700002)(305945005)(189998001)(82746002)(478600001)(36756003)(54906002)(50986999)(99286003)(81166006)(8936002)(8676002)(2900100001)(66066001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0104; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:ovrnspm; PTR:InfoNoRecords; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <4C4E0E5D951DD24782F6345283C5DB2B@eurprd08.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 05 May 2017 08:03:36.6084 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0104 > On 11 Apr 2017, at 16:37, Yao Qi wrote: > > Alan Hayward writes: > > Hi Alan, > There are different ways of getting rid of MAX_REGISTER_SIZE, let us try > some simple approaches first. Some uses of MAX_REGISTER_SIZE still > can't be removed, but let us start from easy part. > Ok, patch split into multiple parts. This part uses the new raw_supply_zeroed. Tested on a --enable-targets=all build using make check with board files unix and native-gdbserver. I do not have a MIPS machine to test on. Ok to commit? 2017-05-05 Alan Hayward * mips-linux-tdep.c (mips_supply_gregset): Use raw_supply_zeroed. (mips_supply_fpregset): Likewise. (mips64_supply_gregset): Likewise. diff --git a/gdb/mips-linux-tdep.c b/gdb/mips-linux-tdep.c index 57e75b5343e1b927e9fe28dea16759f769cf4506..48a582a16c934abe6e8f87c46a6009649c606d49 100644 --- a/gdb/mips-linux-tdep.c +++ b/gdb/mips-linux-tdep.c @@ -133,11 +133,8 @@ mips_supply_gregset (struct regcache *regcache, { int regi; const mips_elf_greg_t *regp = *gregsetp; - char zerobuf[MAX_REGISTER_SIZE]; struct gdbarch *gdbarch = get_regcache_arch (regcache); - memset (zerobuf, 0, MAX_REGISTER_SIZE); - for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); @@ -156,7 +153,7 @@ mips_supply_gregset (struct regcache *regcache, regp + EF_CP0_CAUSE); /* Fill the inaccessible zero register with zero. */ - regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); + regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); } static void @@ -245,9 +242,6 @@ mips_supply_fpregset (struct regcache *regcache, { struct gdbarch *gdbarch = get_regcache_arch (regcache); int regi; - char zerobuf[MAX_REGISTER_SIZE]; - - memset (zerobuf, 0, MAX_REGISTER_SIZE); for (regi = 0; regi < 32; regi++) regcache_raw_supply (regcache, @@ -259,9 +253,8 @@ mips_supply_fpregset (struct regcache *regcache, *fpregsetp + 32); /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ - regcache_raw_supply (regcache, - mips_regnum (gdbarch)->fp_implementation_revision, - zerobuf); + regcache->raw_supply_zeroed + (mips_regnum (gdbarch)->fp_implementation_revision); } static void @@ -379,11 +372,8 @@ mips64_supply_gregset (struct regcache *regcache, { int regi; const mips64_elf_greg_t *regp = *gregsetp; - gdb_byte zerobuf[MAX_REGISTER_SIZE]; struct gdbarch *gdbarch = get_regcache_arch (regcache); - memset (zerobuf, 0, MAX_REGISTER_SIZE); - for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, (const gdb_byte *) (regp + regi)); @@ -407,7 +397,7 @@ mips64_supply_gregset (struct regcache *regcache, (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); /* Fill the inaccessible zero register with zero. */ - regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); + regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); } static void