From patchwork Thu Jan 8 03:47:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 4560 Received: (qmail 14911 invoked by alias); 8 Jan 2015 03:47:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 14890 invoked by uid 89); 8 Jan 2015 03:47:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Jan 2015 03:47:44 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1Y944R-000552-FG from Yao_Qi@mentor.com ; Wed, 07 Jan 2015 19:47:39 -0800 Received: from GreenOnly (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.3.224.2; Wed, 7 Jan 2015 19:47:38 -0800 From: Yao Qi To: "Maciej W. Rozycki" CC: Subject: Re: [PATCH] Recognize branch instruction on MIPS in gdb.trace/entry-values.exp References: <1419840861-10723-1-git-send-email-yao@codesourcery.com> <87zja5uxjk.fsf@codesourcery.com> <87r3vbuecf.fsf@codesourcery.com> <87oaqat6uj.fsf@codesourcery.com> Date: Thu, 8 Jan 2015 11:47:44 +0800 In-Reply-To: (Maciej W. Rozycki's message of "Thu, 8 Jan 2015 01:24:15 +0000") Message-ID: <87fvbmszkv.fsf@codesourcery.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes "Maciej W. Rozycki" writes: > Fair enough, the pattern matches more than necessary, but there are no > MIPS instructions it would match that it shouldn't, so let's keep your > proposal as it is for simplicity. I have no further concerns, thanks for > your work and for getting through this review. Patch below is what I pushed in. Thanks for your review, Maciej. diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 862f27c..2154036 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-01-08 Yao Qi + + * gdb.trace/entry-values.exp: Set call_insn for MIPS target. + 2015-01-07 Jan Kratochvil Fix testcase compilation. diff --git a/gdb/testsuite/gdb.trace/entry-values.exp b/gdb/testsuite/gdb.trace/entry-values.exp index e812241..2548e89 100644 --- a/gdb/testsuite/gdb.trace/entry-values.exp +++ b/gdb/testsuite/gdb.trace/entry-values.exp @@ -43,6 +43,20 @@ if { [istarget "arm*-*-*"] || [istarget "aarch64*-*-*"] } { set call_insn "brasl" } elseif { [istarget "powerpc*-*-*"] } { set call_insn "bl" +} elseif { [istarget "mips*-*-*"] } { + # Skip the delay slot after the instruction used to make a call + # (which can be a jump or a branch) if it has one. + # + # JUMP (or BRANCH) foo + # insn1 + # insn2 + # + # Most MIPS instructions used to make calls have a delay slot. + # These include JAL, JALS, JALX, JALR, JALRS, BAL and BALS. + # In this case the program continues from `insn2' when `foo' + # returns. The only exception is JALRC, in which case execution + # resumes from `insn1' instead. + set call_insn {jalrc|[jb]al[sxr]*[ \t][^\r\n]+\r\n} } else { set call_insn "call" }