From patchwork Mon Jan 18 13:07:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 10420 Received: (qmail 48638 invoked by alias); 18 Jan 2016 13:07:26 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 48629 invoked by uid 89); 18 Jan 2016 13:07:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=svc, Hx-languages-length:6821, Hx-spam-relays-external:209.85.220.67, H*RU:209.85.220.67 X-HELO: mail-pa0-f67.google.com Received: from mail-pa0-f67.google.com (HELO mail-pa0-f67.google.com) (209.85.220.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 18 Jan 2016 13:07:23 +0000 Received: by mail-pa0-f67.google.com with SMTP id gi1so39959087pac.2 for ; Mon, 18 Jan 2016 05:07:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type :content-transfer-encoding; bh=IENk/HvhBKz1A+Dag75XAnZT+CDi/VN2nchG60/Cay4=; b=Dtd2MA6m8/FBFiCEvvXFmNI3irCKD0t3JKpnGENGLoXmRBSjvswiNOMMSPULXkkwdP 3QxJf1qIehK3SguATKgxaLZ/HFu5ug2Hita7hONiEETcu9ip1oZ8bKA3UVpurm/Knn6j c031X3GFNiAi27ZMQOb5sDgAgzPUtb7veqpYRiOVEhZMJ49JAHc29LdqSolTVxUIwCG3 /sthKhM6Uz+iYFQNJ4+CxN51Idci823s+ObQdQTDJxkAqaJQnoTRcll9lXliF8QpIKoT eSCvZMUJl7wiDtkeD4iRAeLih/lRjEpmkduEuWoKUNY0vCKpzAl2I+WfFurVXfHdhk8V 6VuA== X-Gm-Message-State: ALoCoQmjF5tBwqf7wl9uu2FZKhjzS4JxH9GuwOqSlixfnOJTUvy53f5dqcJimA3y5jtzn8Pd8/yTrV4ZdW8pyFTw7Iu0uPBagw== X-Received: by 10.66.158.193 with SMTP id ww1mr36150077pab.21.1453122441257; Mon, 18 Jan 2016 05:07:21 -0800 (PST) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id 73sm28132789pfp.50.2016.01.18.05.07.16 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Mon, 18 Jan 2016 05:07:20 -0800 (PST) From: Yao Qi To: Yao Qi Cc: Antoine Tremblay , Subject: Re: [PATCH v8 3/7] Refactor arm_software_single_step to use regcache References: <1450361684-29536-1-git-send-email-antoine.tremblay@ericsson.com> <1450361684-29536-4-git-send-email-antoine.tremblay@ericsson.com> <86oacjtbue.fsf@gmail.com> Date: Mon, 18 Jan 2016 13:07:11 +0000 In-Reply-To: <86oacjtbue.fsf@gmail.com> (Yao Qi's message of "Mon, 18 Jan 2016 10:34:49 +0000") Message-ID: <86h9ibt4sg.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes Yao Qi writes: > As a record, this patch causes regressions at least in > gdb.base/sigstep.exp, > > (gdb) PASS: gdb.base/sigstep.exp: continue to handler, si+advance in > handler, step from handler: advance in handler > step^M > 39 } /* handler */^M > 1: x/i $pc^M > => 0x8740 : sub sp, r11, #0^M > (gdb) step^M > ^M > Program received signal SIGSEGV, Segmentation fault.^M > setitimer () at ../sysdeps/unix/syscall-template.S:81^M > 81 ../sysdeps/unix/syscall-template.S: No such file or directory.^M > 1: x/i $pc^M > => 0xb6eff9c0 : push {r7}^M > (gdb) FAIL: gdb.base/sigstep.exp: continue to handler, si+advance in > handler, step from handler: leave handler > > Could you take a look at it? Here is my patch fixing the regression in sigstep.exp. The regression test is running now. diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c index 2306bda..f6a831a 100644 --- a/gdb/arm-linux-tdep.c +++ b/gdb/arm-linux-tdep.c @@ -782,10 +782,12 @@ arm_linux_sigreturn_return_addr (struct frame_info *frame, } /* Find the value of the next PC after a sigreturn or rt_sigreturn syscall - based on current processor state. */ + based on current processor state. In addition, set IS_THUMB depending + on whether we will return to ARM or Thumb code. */ + static CORE_ADDR arm_linux_sigreturn_next_pc (struct regcache *regcache, - unsigned long svc_number) + unsigned long svc_number, int *is_thumb) { ULONGEST sp; unsigned long sp_data; @@ -794,6 +796,7 @@ arm_linux_sigreturn_next_pc (struct regcache *regcache, enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int pc_offset = 0; int is_sigreturn = 0; + CORE_ADDR cpsr; gdb_assert (svc_number == ARM_SIGRETURN || svc_number == ARM_RT_SIGRETURN); @@ -807,6 +810,10 @@ arm_linux_sigreturn_next_pc (struct regcache *regcache, next_pc = read_memory_unsigned_integer (sp + pc_offset, 4, byte_order); + /* Set IS_THUMB according the CPSR saved on the stack. */ + cpsr = read_memory_unsigned_integer (sp + pc_offset + 4, 4, byte_order); + *is_thumb = ((cpsr & arm_psr_thumb_bit (gdbarch)) != 0); + return next_pc; } @@ -899,7 +906,12 @@ arm_linux_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, } if (svc_number == ARM_SIGRETURN || svc_number == ARM_RT_SIGRETURN) - next_pc = arm_linux_sigreturn_next_pc (self->regcache, svc_number); + { + /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so + update IS_THUMB. */ + next_pc = arm_linux_sigreturn_next_pc (self->regcache, svc_number, + &is_thumb); + } /* Addresses for calling Thumb functions have the bit 0 set. */ if (is_thumb) diff --git a/gdb/gdbserver/linux-arm-low.c b/gdb/gdbserver/linux-arm-low.c index 927a6fa..01a3bc0 100644 --- a/gdb/gdbserver/linux-arm-low.c +++ b/gdb/gdbserver/linux-arm-low.c @@ -769,16 +769,20 @@ arm_prepare_to_resume (struct lwp_info *lwp) } } -/* Find the next pc for a sigreturn or rt_sigreturn syscall. +/* Find the next pc for a sigreturn or rt_sigreturn syscall. In + addition, set IS_THUMB depending on whether we will return to ARM + or Thumb code. See arm-linux.h for stack layout details. */ static CORE_ADDR -arm_sigreturn_next_pc (struct regcache *regcache, int svc_number) +arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, + int *is_thumb) { unsigned long sp; unsigned long sp_data; /* Offset of PC register. */ int pc_offset = 0; CORE_ADDR next_pc = 0; + CORE_ADDR cpsr; gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); @@ -790,6 +794,10 @@ arm_sigreturn_next_pc (struct regcache *regcache, int svc_number) (*the_target->read_memory) (sp + pc_offset, (unsigned char *) &next_pc, 4); + /* Set IS_THUMB according the CPSR saved on the stack. */ + (*the_target->read_memory) (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); + *is_thumb = ((cpsr & CPSR_T) != 0); + return next_pc; } @@ -831,7 +839,9 @@ get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, CORE_ADDR pc) /* This is a sigreturn or sigreturn_rt syscall. */ if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) { - next_pc = arm_sigreturn_next_pc (regcache, svc_number); + /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so + update IS_THUMB. */ + next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); } /* Addresses for calling Thumb functions have the bit 0 set. */