diff mbox

New ARI warning Wed May 27 01:54:00 UTC 2015

Message ID 864mmyqpew.fsf@gmail.com
State New
Headers show

Commit Message

Yao Qi May 27, 2015, 10:35 a.m. UTC
GDB Administrator <gdbadmin@sourceware.org> writes:

> 0a1,4
>> gdb/aarch64-tdep.c:3009: code: OP eol: Do not use &&, or || at the
>> end of a line
> gdb/aarch64-tdep.c:3009: if (!bits (aarch64_insn_r->aarch64_insn, 2,
> 4) &&
>> gdb/aarch64-tdep.c:3010: code: OP eol: Do not use &&, or || at the
>> end of a line
> gdb/aarch64-tdep.c:3010: !bits (aarch64_insn_r->aarch64_insn, 21, 23)
> &&
>> gdb/aarch64-tdep.c:3413: code: OP eol: Do not use &&, or || at the
>> end of a line
> gdb/aarch64-tdep.c:3413: else if ((insn_bits24_27 & 0x0b) == 0x08 &&
> insn_bits28_29 == 0x03 &&
>> gdb/aarch64-tdep.c:3460: code: OP eol: Do not use &&, or || at the
>> end of a line
> gdb/aarch64-tdep.c:3460: else if ((insn_bits24_27 & 0x0b) == 0x08 &&
> insn_bits28_29 == 0x03 &&

Here is the patch to fix these warnings...  I'll push it in.
diff mbox

Patch

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index d07b26c..9650a7a 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -3006,9 +3006,9 @@  aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
       /* Exception generation instructions. */
       if (insn_bits24_27 == 0x04)
 	{
-	  if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) &&
-	      !bits (aarch64_insn_r->aarch64_insn, 21, 23) &&
-	      bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
+	  if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
+	      && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
+	      && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
 	    {
 	      ULONGEST svc_number;
 
@@ -3410,8 +3410,8 @@  aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
         }
     }
   /* Load/store register (register offset) instructions.  */
-  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
-	   insn_bits10_11 == 0x02 && insn_bit21)
+  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+	   && insn_bits10_11 == 0x02 && insn_bit21)
     {
       if (record_debug)
 	{
@@ -3457,8 +3457,8 @@  aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
         }
     }
   /* Load/store register (immediate and unprivileged) instructions.  */
-  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
-          !insn_bit21)
+  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+	   && !insn_bit21)
     {
       if (record_debug)
 	{