From patchwork Thu Dec 13 20:57:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 30665 Received: (qmail 38550 invoked by alias); 13 Dec 2018 20:58:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38391 invoked by uid 89); 13 Dec 2018 20:58:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Gm-Message-State:aEWb, gdb's, GDB's, gdbs X-HELO: mail-wm1-f65.google.com Received: from mail-wm1-f65.google.com (HELO mail-wm1-f65.google.com) (209.85.128.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Dec 2018 20:57:58 +0000 Received: by mail-wm1-f65.google.com with SMTP id a18so3813358wmj.1 for ; Thu, 13 Dec 2018 12:57:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=WRe+CgG/8vK4m5lHIjdVpq83SW8nmY6rQ1IbE2YogLc=; b=NlaqGbddzFb+tReW0vEcNkIZXg4ErBqVNkzNMMUd4Ig7CLlQb4R9NnsOa6MfyTC5dl L3uvCzgr2oHFD+0Uo4mBQk4SNlt1AfSKRtr96zklgbtpI7wVevBKjlk1R4r27C1thmZE McTPfJjyphRb/hb22Qh+8KB39aiHhG6wK7xJMXSqUP+THyFFvL5f6blDjHIW3R1/6ZCc OwThZqpWd2pgVTLr1IReAQylWVfCLwmmwlKjf0gWWJ8R/ZzTdJ/iO/1pg3aTH/ZezZuN BHTp0DZGtG4Hv4aGgDrC7Y+tGcpWxN86vZv29Nu9qRUOdHbyYV7awwJnO1EhUXliAGjH Vgnw== Return-Path: Received: from localhost ([176.12.107.132]) by smtp.gmail.com with ESMTPSA id h12sm5204586wma.48.2018.12.13.12.57.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 12:57:55 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org Cc: jimw@sifive.com, palmer@sifive.com, jhb@FreeBSD.org, Andrew Burgess Subject: [PATCH 1/2] gdb/riscv: Add gdb to dwarf register number mapping Date: Thu, 13 Dec 2018 20:57:49 +0000 Message-Id: <227d9aa969b2dde68317bb1efffae5121a068737.1544734579.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes Provide a mapping between GDB's register numbers and DWARF's register numbers. This resolves some failures that I was seeing on gdb.base/store.exp when running on an rv64imfdc target. gdb/ChangeLog: * riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function. (riscv_gdbarch_init): Register new function with gdbarch. * riscv-tdep.h: New enum to define RISC-V DWARF register numbers. --- gdb/ChangeLog | 6 ++++++ gdb/riscv-tdep.c | 17 +++++++++++++++++ gdb/riscv-tdep.h | 9 +++++++++ 3 files changed, 32 insertions(+) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 88b79af866f..3b737064612 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -2940,6 +2940,20 @@ riscv_setup_register_aliases (struct gdbarch *gdbarch, } } +/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ + +static int +riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) +{ + if (reg < RISCV_DWARF_REGNUM_X31) + return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); + + else if (reg < RISCV_DWARF_REGNUM_F31) + return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); + + return -1; +} + /* Initialize the current architecture based on INFO. If possible, re-use an architecture from ARCHES, which is a list of architectures already created during this debugging session. @@ -3127,6 +3141,9 @@ riscv_gdbarch_init (struct gdbarch_info info, /* Register architecture. */ riscv_add_reggroups (gdbarch); + /* Internal <-> external register number maps. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum); + /* We reserve all possible register numbers for the known registers. This means the target description mechanism will add any target specific registers after this number. This helps make debugging GDB diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index 59ad37df6ce..b564a58e96c 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -56,6 +56,15 @@ enum RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM }; +/* RiscV DWARF register numbers. */ +enum +{ + RISCV_DWARF_REGNUM_X0 = 0, + RISCV_DWARF_REGNUM_X31 = 31, + RISCV_DWARF_REGNUM_F0 = 32, + RISCV_DWARF_REGNUM_F31 = 63, +}; + /* RISC-V specific per-architecture information. */ struct gdbarch_tdep {